From: yxj Date: Sat, 8 Sep 2012 08:50:04 +0000 (+0800) Subject: rk3066b lcdc: rename rk31 to rk3066b X-Git-Tag: firefly_0821_release~8685 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1f9f2249d553f7357ac792f0fad1a05dcc4eb170;p=firefly-linux-kernel-4.4.55.git rk3066b lcdc: rename rk31 to rk3066b --- diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index a538dc8865c8..ec333509658d 100755 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -59,23 +59,23 @@ config LCDC1_RK30 help Support rk30 lcdc1 if you say y here -config LCDC_RK31 - tristate "rk3066b/rk31 lcdc support" +config LCDC_RK3066B + tristate "rk3066b lcdc support" depends on FB_ROCKCHIP && ARCH_RK3066B help - Driver for rk3066b/rk31 lcdc. + Driver for rk3066b lcdc. -config LCDC0_RK31 +config LCDC0_RK3066B bool "lcdc0 support" - depends on LCDC_RK31 + depends on LCDC_RK3066B default y help Support lcdc0 if you say y here -config LCDC1_RK31 +config LCDC1_RK3066B bool "lcdc1 support" - depends on LCDC_RK31 - default y if HDMI_RK31 + depends on LCDC_RK3066B + default n help Support lcdc1 if you say y here diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 0f1a3880879e..4c70ad1e4176 100755 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -1,8 +1,8 @@ obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o rkfb_sysfs.o obj-$(CONFIG_FB_WIMO) +=wimo.o -obj-$(CONFIG_LCDC_RK30) += chips/rk30_lcdc.o -obj-$(CONFIG_LCDC_RK2928) += chips/rk2928_lcdc.o -obj-$(CONFIG_LCDC_RK31) += chips/rk31_lcdc.o +obj-$(CONFIG_LCDC_RK30) += lcdc/rk30_lcdc.o +obj-$(CONFIG_LCDC_RK2928) += lcdc/rk2928_lcdc.o +obj-$(CONFIG_LCDC_RK3066B) += lcdc/rk3066b_lcdc.o obj-$(CONFIG_RGA_RK30) += rga/ obj-$(CONFIG_RK_HDMI) += hdmi/ obj-$(CONFIG_RK_LVDS) += lvds/ diff --git a/drivers/video/rockchip/chips/rk2928_lcdc.c b/drivers/video/rockchip/chips/rk2928_lcdc.c deleted file mode 100755 index c991c1c62d95..000000000000 --- a/drivers/video/rockchip/chips/rk2928_lcdc.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * drivers/video/rockchip/chips/rk2928_lcdc.c - * - * Copyright (C) 2012 ROCKCHIP, Inc. - *Author:yzq - * yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk2928_lcdc.h" -#include "../lvds/rk_lvds.h" - - - - - -static int dbg_thresd = 2; -module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); -#define DBG(level,x...) do { if(unlikely(dbg_thresd > level)) printk(KERN_INFO x); } while (0) - - -static int init_rk2928_lcdc(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - if(lcdc_dev->id == 0) //lcdc0 - { - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); - lcdc_dev->sclk = clk_get(NULL,"sclk_lcdc0"); - } - else - { - printk(KERN_ERR "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->sclk) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) - { - printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); - } - - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config - clk_enable(lcdc_dev->aclk); - lcdc_dev->clk_on = 1; - LcdSetBit(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | - m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | - v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync - //LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - return 0; -} - -static int rk2928_lcdc_deinit(struct rk2928_lcdc_device *lcdc_dev) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LcdMskReg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN | - m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) | - v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt - LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - mdelay(1); - - return 0; -} - -static int rk2928_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - rk_screen *screen = dev_drv->cur_screen; - rk_screen *screen0 = dev_drv->screen0; - u64 ft; - int fps; - u16 face; - u16 right_margin = screen->right_margin; - u16 lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - DBG(1,"left_margin:%d>>hsync_len:%d>>xres:%d>>right_margin:%d>>upper_margin:%d>>vsync_len:%d>>yres:%d>>lower_margin:%d\n", - screen->left_margin,screen->hsync_len,screen->x_res,screen->right_margin,screen->upper_margin,screen->vsync_len,screen->y_res, - screen->lower_margin); - // set the rgb or mcu - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(screen->type==SCREEN_MCU) - { - printk(KERN_ERR "MCU Screen is not supported by RK2928\n"); - - } - - switch (screen->face) - { - case OUT_P565: - face = OUT_P565; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_P666: - face = OUT_P666; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_D888_P565: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_D888_P666: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_P888: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - break; - default: - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - face = screen->face; - break; - } - - //use default overlay,set vsyn hsync den dclk polarity - LcdMskReg(lcdc_dev, DSP_CTRL,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | - m_DEN_POLARITY |m_DCLK_POLARITY | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_BLACK_MODE, - v_DISPLAY_FORMAT(face) | v_HSYNC_POLARITY(screen->pin_hsync) | - v_VSYNC_POLARITY(screen->pin_vsync) | v_DEN_POLARITY(screen->pin_den) | - v_DCLK_POLARITY(screen->pin_dclk) | v_OUTPUT_RB_SWAP(screen->swap_rb) | - v_OUTPUT_RG_SWAP(screen->swap_rg) |v_BLACK_MODE(0)); - - //set background color to black,set swap according to the screen panel,disable blank mode - LcdMskReg(lcdc_dev, BG_COLOR, m_BG_COLOR ,v_BG_COLOR(0x000000)); - - - LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | - v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); - LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | - v_HASP(screen->hsync_len + screen->left_margin)); - - LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | - v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| - v_VASP(screen->vsync_len + screen->upper_margin)); - - - if(dev_drv->screen0->lcdc_id == 1) - { - //set register for scaller - LcdMskReg(lcdc_dev,SCL_REG0,m_SCL_DSP_ZERO | m_SCL_DEN_INVERT | - m_SCL_SYNC_INVERT | m_SCL_DCLK_INVERT | m_SCL_EN,v_SCL_DSP_ZERO(0) | - v_SCL_DEN_INVERT(screen0->s_den_inv) | v_SCL_SYNC_INVERT(screen0->s_hv_sync_inv) | - v_SCL_DCLK_INVERT(screen0->s_clk_inv) | v_SCL_EN(1)); - LcdWrReg(lcdc_dev,SCL_REG2,v_HASP(screen0->s_vsync_st) | v_HAEP(screen0->s_hsync_st)); - LcdWrReg(lcdc_dev,SCL_REG3,v_HASP(screen0->s_hsync_len) | - v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + - screen0->x_res + screen0->s_right_margin)); - LcdWrReg(lcdc_dev,SCL_REG4,v_HASP(screen0->s_hsync_len + screen0->s_left_margin) | - v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + screen0->x_res)); - LcdWrReg(lcdc_dev,SCL_REG5,v_VASP(screen0->s_vsync_len) | - v_VAEP(screen0->s_vsync_len + screen0->s_upper_margin + - screen0->y_res + screen0->s_lower_margin)); - LcdWrReg(lcdc_dev,SCL_REG6,v_VASP(screen0->s_vsync_len + - screen0->s_upper_margin) | v_VAEP(screen0->s_vsync_len + - screen0->s_upper_margin + screen0->y_res )); - LcdWrReg(lcdc_dev,SCL_REG8,v_VASP(screen0->s_vsync_len + screen0->s_upper_margin) | - v_VAEP(screen0->s_vsync_len + screen0->s_upper_margin + screen0->y_res)); - LcdWrReg(lcdc_dev,SCL_REG7,v_HASP(screen0->s_hsync_len + screen0->s_left_margin) | - v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + screen0->x_res )); - LcdWrReg(lcdc_dev,SCL_REG1,v_SCL_V_FACTOR(0x1000)|v_SCL_H_FACTOR(0x1000)); - } - // let above to take effect - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - -#ifdef CONFIG_RK_LVDS - rk_lvds_register(dev_drv->screen0); -#endif - if(dev_drv->screen0->type == SCREEN_RGB) //iomux for RGB screen - { - - if(dev_drv->screen0->lcdc_id == 0) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC0_DCLK); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC0_HSYNC); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC0_VSYNC); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC0_DEN); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC0_D10); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC0_D11); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC0_D12); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC0_D13); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC0_D14); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC0_D15); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC0_D16); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC0_D17); - } - else if(dev_drv->screen0->lcdc_id == 1) - { - rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC1_DCLK); - rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC1_HSYNC); - rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC1_VSYNC); - rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC1_DEN); - rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC1_D10); - rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC1_D11); - rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC1_D12); - rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC1_D13); - rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC1_D14); - rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC1_D15); - rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC1_D16); - rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC1_D17); - } - else - { - printk(KERN_WARNING "%s>>>no such interface:%d\n",dev_drv->cur_screen->lcdc_id); - return -1; - } - - //rk30_mux_api_set(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME, GPIO2C_LCDC1_D18); - //rk30_mux_api_set(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME, GPIO2C_LCDC1_D19); - //rk30_mux_api_set(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME, GPIO2C_LCDC1_D20); - //rk30_mux_api_set(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME, GPIO2C_LCDC1_D21); - //rk30_mux_api_set(GPIO2D0_LCDC0_D22_LCDC1_D22_NAME, GPIO2D_LCDC1_D22); - //rk30_mux_api_set(GPIO2D1_LCDC0_D23_LCDC1_D23_NAME, GPIO2D_LCDC1_D23); - printk("RGB screen connect to rk2928 lcdc interface%d\n",dev_drv->screen0->lcdc_id); - - } - - ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - clk_enable(lcdc_dev->dclk); - if(dev_drv->screen0->lcdc_id == 1) //if connect to output interface 1,need scale - { - ret = clk_set_rate(lcdc_dev->sclk, screen0->s_pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d sclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->sclk)); - //printk("%s: sclk:%lu>>need:%d",lcdc_dev->driver.name,,screen0->s_pixclock); - clk_enable(lcdc_dev->sclk); - } - - - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps; - printk("%s: dclk:%lu>>sclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk), - clk_get_rate(lcdc_dev->sclk),fps); - - if(screen->init) - { - screen->init(); - } - - printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); - return 0; -} - - -//enable layer,open:1,enable;0 disable -static int win0_open(struct rk2928_lcdc_device *lcdc_dev,bool open) -{ - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[0]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} -static int win1_open(struct rk2928_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); - LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); - LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - } - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} - - -static int rk2928_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) -{ - struct rk2928_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk2928_lcdc_device ,driver); - - printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(0)); - break; - case FB_BLANK_NORMAL: - LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - default: - LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr); - LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN1_RGB_MST, y_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - - xact = par->xact; //active (origin) picture window width/height - yact = par->yact; - xvir = par->xvir; // virtual resolution - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor - ScaleYrgbY = CalScale(yact, par->ysize); - switch (par->format) - { - case YUV422:// yuv422 - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - break; - } - - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); - LcdMskReg(lcdc_dev, SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(par->format)); //(inf->video_mode==0) - LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); - LcdMskReg(lcdc_dev,WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, - v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case ARGB888: - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_ARGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1)); - break; - case RGB565: //rgb565 - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB565_VIRWIDTH(xvir)); - break; - case YUV422: - case YUV420: - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_YUV_VIRWIDTH(xvir)); - break; - default: - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir)); - break; - } - - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(par->format)); - LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - - - switch(par->format) - { - case ARGB888: - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir)); - // LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB565: //rgb565 - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB565_VIRWIDTH(xvir)); - break; - default: - LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir)); - break; - } - - - //LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk2928_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - if(layer_id == 0) - { - win0_open(lcdc_dev,open); - } - else if(layer_id == 1) - { - win1_open(lcdc_dev,open); - } - - return 0; -} - -static int rk2928_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - rk_screen *screen0 = dev_drv->screen0; - u32 Scl_X = 0x1000; - u32 Scl_Y = 0x1000; - - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_set_par(lcdc_dev,screen,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_set_par(lcdc_dev,screen,par); - } - Scl_X = CalScale(screen->x_res - 1,screen0->x_res - 1); - Scl_Y = CalScale(screen->y_res - 1 ,screen0->y_res - 1); - LcdWrReg(lcdc_dev,SCL_REG1,v_SCL_V_FACTOR(Scl_Y)|v_SCL_H_FACTOR(Scl_X)); - - return 0; -} - -int rk2928_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - unsigned long flags; - int timeout; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_display(lcdc_dev,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_display(lcdc_dev,par); - } - if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt - { - dev_drv->first_frame = 0; - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN , - v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1)); - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - - } - - if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn - { - spin_lock_irqsave(&dev_drv->cpl_lock,flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); - if(!timeout&&(!dev_drv->frame_done.done)) - { - //printk(KERN_ERR "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -int rk2928_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - int ret = 0; - switch(cmd) - { - case FBIOGET_PANEL_SIZE: //get panel size - panel_size[0] = lcdc_dev->screen->x_res; - panel_size[1] = lcdc_dev->screen->y_res; - if(copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - default: - break; - } - - return ret; -} -static int rk2928_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - struct layer_par *par = dev_drv->layer_par[layer_id]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(layer_id == 0) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN); - } - else if( layer_id == 1) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return par->state; - -} - -/*********************************** -overlay manager -swap:1 win0 on the top of win1 - 0 win1 on the top of win0 -set : 1 set overlay - 0 get overlay state -************************************/ -static int rk2928_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(set) //set overlay - { - LcdMskReg(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); - LCDC_REG_CFG_DONE(); - ovl = swap; - } - else //get overlay - { - ovl = LcdReadBit(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP); - } - } - else - { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} -static int rk2928_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - return 0; -} - - -/******************************************* -lcdc fps manager,set or get lcdc fps -set:0 get - 1 set -********************************************/ -static int rk2928_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - rk_screen * screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - - if(set) - { - ft = div_u64(1000000000000llu,fps); - dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); - dotclk = div_u64(1000000000000llu,dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - } - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps ; //one frame time in ms - return fps; -} - - -static int rk2928_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if(order == FB_DEFAULT_ORDER) - { - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - } - dev_drv->fb2_win_id = order/100; - dev_drv->fb1_win_id = (order/10)%10; - dev_drv->fb0_win_id = order%10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, - dev_drv->fb2_win_id); - - return 0; -} - -static int rk2928_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) -{ - int layer_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if(!strcmp(id,"fb0")) - { - layer_id = dev_drv->fb0_win_id; - } - else if(!strcmp(id,"fb1")) - { - layer_id = dev_drv->fb1_win_id; - } - else if(!strcmp(id,"fb2")) - { - layer_id = dev_drv->fb2_win_id; - } - else - { - printk(KERN_ERR "%s>>un supported %s\n",__func__,id); - layer_id = -1; - } - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return layer_id; -} - -int rk2928_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - - if(dev_drv->cur_screen->sscreen_set) - dev_drv->cur_screen->sscreen_set(dev_drv->cur_screen , 0); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - - mdelay(1); - clk_disable(lcdc_dev->dclk); - clk_disable(lcdc_dev->hclk); - clk_disable(lcdc_dev->aclk); - clk_disable(lcdc_dev->pd); - - return 0; -} - - -int rk2928_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); - - if(!lcdc_dev->clk_on) - { - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); - clk_enable(lcdc_dev->dclk); - clk_enable(lcdc_dev->aclk); - } - memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->atv_layer_cnt) - { - LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - } - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - - - if(dev_drv->cur_screen->sscreen_set) - dev_drv->cur_screen->sscreen_set(dev_drv->cur_screen , 1); - - - return 0; -} -static irqreturn_t rk2928_lcdc_isr(int irq, void *dev_id) -{ - struct rk2928_lcdc_device *lcdc_dev = (struct rk2928_lcdc_device *)dev_id; - - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LCDC_REG_CFG_DONE(); - //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); - - if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync - { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - return IRQ_HANDLED; -} - -static struct layer_par lcdc_layer[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, -}; - -static struct rk_lcdc_device_driver lcdc_driver = { - .name = "lcdc", - .def_layer_par = lcdc_layer, - .num_layer = ARRAY_SIZE(lcdc_layer), - .open = rk2928_lcdc_open, - .init_lcdc = init_rk2928_lcdc, - .ioctl = rk2928_lcdc_ioctl, - .suspend = rk2928_lcdc_early_suspend, - .resume = rk2928_lcdc_early_resume, - .set_par = rk2928_lcdc_set_par, - .blank = rk2928_lcdc_blank, - .pan_display = rk2928_lcdc_pan_display, - .load_screen = rk2928_load_screen, - .get_layer_state = rk2928_lcdc_get_layer_state, - .ovl_mgr = rk2928_lcdc_ovl_mgr, - .get_disp_info = rk2928_lcdc_get_disp_info, - .fps_mgr = rk2928_lcdc_fps_mgr, - .fb_get_layer = rk2928_fb_get_layer, - .fb_layer_remap = rk2928_fb_layer_remap, -}; -#ifdef CONFIG_PM -static int rk2928_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk2928_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} - -#else -#define rk2928_lcdc_suspend NULL -#define rk2928_lcdc_resume NULL -#endif - -static int __devinit rk2928_lcdc_probe (struct platform_device *pdev) -{ - struct rk2928_lcdc_device *lcdc_dev=NULL; - rk_screen *screen0; - rk_screen *screen1; - struct rk29fb_info *screen_ctr_info; - struct resource *res = NULL; - struct resource *mem; - int ret = 0; - - /*************Malloc rk2928lcdc_inf and set it to pdev for drvdata**********/ - lcdc_dev = kzalloc(sizeof(struct rk2928_lcdc_device), GFP_KERNEL); - if(!lcdc_dev) - { - dev_err(&pdev->dev, ">>rk2928 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->id = pdev->id; - screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; - screen0 = kzalloc(sizeof(rk_screen), GFP_KERNEL); //rk2928 has one lcdc but two outputs - if(!screen0) - { - dev_err(&pdev->dev, ">>rk2928 lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen0->lcdc_id = 0; //this id can be changed dynamic - screen0->screen_id = 0; //this id is fixed - screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen1) - { - dev_err(&pdev->dev, ">>rk2928 lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen1->lcdc_id = 1; - screen1->screen_id = 1; - - /****************get lcdc0 reg *************************/ - res = platform_get_resource(pdev, IORESOURCE_MEM,0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); - if (lcdc_dev->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "cannot map IO\n"); - ret = -ENXIO; - goto err2; - } - - lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; - printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); - lcdc_dev->driver.dev=&pdev->dev; - lcdc_dev->driver.screen0 = screen0; //direct out put - lcdc_dev->driver.screen1 = screen1; //out put from scale - lcdc_dev->driver.cur_screen = screen0; - lcdc_dev->driver.screen_ctr_info = screen_ctr_info; - spin_lock_init(&lcdc_dev->reg_lock); - lcdc_dev->irq = platform_get_irq(pdev, 0); - if(lcdc_dev->irq < 0) - { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err3; - } - ret = request_irq(lcdc_dev->irq, rk2928_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); - if (ret) - { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); - ret = -EBUSY; - goto err3; - } - ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); - if(ret < 0) - { - printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); - goto err4; - } - printk("rk2928 lcdc%d probe ok!\n",lcdc_dev->id); - - return 0; - -err4: - free_irq(lcdc_dev->irq,lcdc_dev); -err3: - iounmap(lcdc_dev->reg_vir_base); -err2: - release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); -err1: - kfree(screen0); -err0: - platform_set_drvdata(pdev, NULL); - kfree(lcdc_dev); - return ret; - -} -static int __devexit rk2928_lcdc_remove(struct platform_device *pdev) -{ - struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk_fb_unregister(&(lcdc_dev->driver)); - rk2928_lcdc_deinit(lcdc_dev); - iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev); - return 0; -} - -static void rk2928_lcdc_shutdown(struct platform_device *pdev) -{ - struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary - lcdc_dev->driver.cur_screen->standby(1); - if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary - lcdc_dev->driver.screen_ctr_info->io_disable(); - if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds - lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); - rk_fb_unregister(&(lcdc_dev->driver)); - rk2928_lcdc_deinit(lcdc_dev); - /*iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev);*/ -} - - -static struct platform_driver rk2928lcdc_driver = { - .probe = rk2928_lcdc_probe, - .remove = __devexit_p(rk2928_lcdc_remove), - .driver = { - .name = "rk2928-lcdc", - .owner = THIS_MODULE, - }, - .suspend = rk2928_lcdc_suspend, - .resume = rk2928_lcdc_resume, - .shutdown = rk2928_lcdc_shutdown, -}; - -static int __init rk2928_lcdc_init(void) -{ - return platform_driver_register(&rk2928lcdc_driver); -} - -static void __exit rk2928_lcdc_exit(void) -{ - platform_driver_unregister(&rk2928lcdc_driver); -} - - - -fs_initcall(rk2928_lcdc_init); -module_exit(rk2928_lcdc_exit); - - - diff --git a/drivers/video/rockchip/chips/rk2928_lcdc.h b/drivers/video/rockchip/chips/rk2928_lcdc.h deleted file mode 100755 index caa60b8d048e..000000000000 --- a/drivers/video/rockchip/chips/rk2928_lcdc.h +++ /dev/null @@ -1,519 +0,0 @@ -#ifndef RK2928_LCDC_H_ -#define RK2928_LCDC_H_ - -#include - -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) -#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ - -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CFG; //0x00 system config register - unsigned int DSP_CTRL; //0x0c display control register - unsigned int BG_COLOR; //back ground color register - unsigned int ALPHA_CTRL; //alpha control register - unsigned int INT_STATUS; //0x10 Interrupt status register - unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register - unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0 - unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0 - unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height - unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height - unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel - unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel - unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset - unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address - unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel - unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel - unsigned int HWC_MST; //0x88 HWC memory start address - unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point - unsigned int SCL_REG0; //scaler register - unsigned int SCL_REG1; - unsigned int SCL_REG2; - unsigned int SCL_REG3; - unsigned int SCL_REG4; - unsigned int SCL_REG5; - unsigned int SCL_REG6; - unsigned int SCL_REG7; - unsigned int SCL_REG8; - unsigned int reserve[3]; - unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH - -} LCDC_REG, *pLCDC_REG; - - -/* SYS_CONFIG */ - -#define m_W0_EN (1<<0) -#define m_W1_EN (1<<1) -#define m_HWC_EN (1<<2) -#define m_W0_FORMAT (7<<3) -#define m_W1_FORMAT (7<<6) - -#define m_W0_AXI_OUTSTANDING_DISABLE (1<<16) -#define m_W1_AXI_OUTSTANDING_DISABLE (1<<17) -#define m_DMA_BURST_LENGTH (3<<18) -#define m_LCDC_STANDBY (1<<22) - -#define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power - -#define v_W0_EN(x) (((x)&1)<<0) -#define v_W1_EN(x) (((x)&1)<<1) -#define v_HWC_EN(x) (((x)&1)<<2) -#define v_W0_FORMAT(x) (((x)&7)<<3) -#define v_W1_FORMAT(x) (((x)&7)<<6) -#define v_LCDC_STANDBY(x) (((x)&1)<<22) - -#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24) - -#define v_LCDC_DMA_STOP(x) (((x)&1)<<0) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<2) -#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3) -#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4) -#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6) -#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8) -#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11) -#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14) -#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17) -#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20) -#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23) -#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26) -#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29) - - - -//LCDC_DSP_CTRL_REG -#define m_DISPLAY_FORMAT (3<<0) -#define m_BLANK_MODE (1<<2) -#define m_BLACK_MODE (1<<3) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_W0W1_POSITION_SWAP (1<<8) -#define m_OUTPUT_BG_SWAP (1<<9) -#define m_OUTPUT_RB_SWAP (1<<10) -#define m_OUTPUT_RG_SWAP (1<<11) -#define m_DITHER_UP_EN (1<<12) -#define m_DITHER_DOWN_MODE (1<<13) -#define m_DITHER_DOWN_EN (1<<14) - - -#define m_W1_INTERLACE_READ_MODE (1<<15) -#define m_W2_INTERLACE_READ_MODE (1<<16) -#define m_W0_YRGB_DEFLICK_MODE (1<<17) -#define m_W0_CBR_DEFLICK_MODE (1<<18) -#define m_W1_YRGB_DEFLICK_MODE (1<<19) -#define m_W1_CBR_DEFLICK_MODE (1<<20) -#define m_W0_ALPHA_MODE (1<<21) -#define m_W1_ALPHA_MODE (1<<22) -#define m_W2_ALPHA_MODE (1<<23) -#define m_W0_COLOR_SPACE_CONVERSION (3<<24) -#define m_W1_COLOR_SPACE_CONVERSION (3<<26) -#define m_W2_COLOR_SPACE_CONVERSION (1<<28) -#define m_YCRCB_CLIP_EN (1<<29) -#define m_CBR_FILTER_656 (1<<30) - -#define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0) -#define v_BLANK_MODE(x) (((x)&1)<<2) -#define v_BLACK_MODE(x) (((x)&1)<<2) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11) -#define v_DITHER_UP_EN(x) (((x)&1)<<12) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<13) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<14) - -#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) -#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14) -#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15) -#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16) -#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17) -#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18) -#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19) -#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20) -#define v_W0_ALPHA_MODE(x) (((x)&1)<<21) -#define v_W1_ALPHA_MODE(x) (((x)&1)<<22) -#define v_W2_ALPHA_MODE(x) (((x)&1)<<23) -#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24) -#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26) -#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28) -#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29) -#define v_CBR_FILTER_656(x) (((x)&1)<<30) - -//LCDC_BG_COLOR -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) - - - - -//LCDC_ BLEND_CTRL -#define m_HWC_BLEND_EN (1<<0) -#define m_W2_BLEND_EN (1<<1) -#define m_W1_BLEND_EN (1<<2) -#define m_W0_BLEND_EN (1<<3) -#define m_HWC_BLEND_FACTOR (15<<4) -#define m_W2_BLEND_FACTOR (0xff<<8) -#define m_W1_BLEND_FACTOR (0xff<<16) -#define m_W0_BLEND_FACTOR (0xff<<24) - -#define v_HWC_BLEND_EN(x) (((x)&1)<<0) -#define v_W2_BLEND_EN(x) (((x)&1)<<1) -#define v_W1_BLEND_EN(x) (((x)&1)<<2) -#define v_W0_BLEND_EN(x) (((x)&1)<<3) -#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) -#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) - -//LCDC_INT_STATUS -#define v_HOR_START_INT_STA (1<<0) //status -#define v_FRM_START_INT_STA (1<<1) -#define v_LINE_FLAG_INT_STA (1<<2) -#define v_BUS_ERR_INT_STA (1<<3) -#define m_HOR_START_INT_EN (1<<4) //enable -#define m_FRM_START_INT_EN (1<<5) -#define m_LINE_FLAG_INT_EN (1<<6) -#define m_BUS_ERR_INT_EN (1<<7) -#define m_HOR_START_INT_CLEAR (1<<8) //auto clear -#define m_FRM_START_INT_CLEAR (1<<9) -#define m_LINE_FLAG_INT_CLEAR (1<<10) -#define m_BUS_ERR_INT_CLEAR (1<<11) -#define m_LINE_FLAG_NUM (0xfff<<12) -#define v_HOR_START_INT_EN(x) (((x)&1)<<4) -#define v_FRM_START_INT_EN(x) (((x)&1)<<5) -#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6) -#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) -#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8) -#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9) -#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10) -#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) -#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) - - -//LCDC_WIN_VIR -#define m_WIN0_VIR (0xfff << 0) -#define m_WIN1_VIR (0xfff << 16) -//LCDC_WINx_VIR ,x is number of words of win0 virtual width -#define v_WIN0_ARGB888_VIRWIDTH(x) (x) -#define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3)) -#define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0)) -#define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0)) - -#define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16) -#define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16) -#define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16) -#define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 ) - - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - - - - - -//AXI MS ID -#define m_W0_YRGB_CH_ID (0xF<<0) -#define m_W0_CBR_CH_ID (0xF<<4) -#define m_W1_YRGB_CH_ID (0xF<<8) -#define m_W2_CH_ID (0xF<<12) -#define m_HWC_CH_ID (0xF<<16) -#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) -#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) -#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) -#define v_W2_CH_ID(x) (((x)&0xF)<<12) -#define v_HWC_CH_ID(x) (((x)&0xF)<<16) - - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - - -//LCDC_WINx_SCL_FACTOR_Y/CBCR -#define v_X_SCL_FACTOR(x) ((x)<<0) -#define v_Y_SCL_FACTOR(x) ((x)<<16) - -//LCDC_DSP_HTOTAL_HS_END -#define v_HSYNC(x) ((x)<<0) //hsync pulse width -#define v_HORPRD(x) ((x)<<16) //horizontal period - - -//LCDC_DSP_HACT_ST_END -#define v_HAEP(x) ((x)<<0) //horizontal active end point -#define v_HASP(x) ((x)<<16) //horizontal active start point - -//LCDC_DSP_VTOTAL_VS_END -#define v_VSYNC(x) ((x)<<0) -#define v_VERPRD(x) ((x)<<16) - -//LCDC_DSP_VACT_ST_END -#define v_VAEP(x) ((x)<<0) -#define v_VASP(x) ((x)<<16) - - - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_WIN0_ACT_INFO -#define v_ACT_WIDTH(x) ((x-1)<<0) -#define v_ACT_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_INFO -#define v_DSP_WIDTH(x) ((x-1)<<0) -#define v_DSP_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning -#define v_DSP_STX(x) (x<<0) -#define v_DSP_STY(x) (x<<16) - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - -//LCDC_SCL_REG0 -#define m_SCL_DSP_ZERO (1<<4) -#define m_SCL_DEN_INVERT (1<<3) -#define m_SCL_SYNC_INVERT (1<<2) -#define m_SCL_DCLK_INVERT (1<<1) -#define m_SCL_EN (1<<0) -#define v_SCL_DSP_ZERO(x) (((x)&1)<<4) -#define v_SCL_DEN_INVERT(x) (((x)&1)<<3) -#define v_SCL_SYNC_INVERT(x) (((x)&1)<<2) -#define v_SCL_DCLK_INVERT(x) (((x)&1)<<1) -#define v_SCL_EN(x) (((x)&1)<<0) - -//LCDC_SCL_REG1 -#define m_SCL_V_FACTOR (0x3fff<<16) -#define m_SCL_H_FACTOR (0x3fff<<0) -#define v_SCL_V_FACTOR(x) (((x)&0x3fff)<<16) -#define v_SCL_H_FACTOR(x) (((x)&0x3fff)<<0) - - -//LCDC_SCL_REG2 -#define m_SCL_DSP_FRAME_VST (0xfff<<16) -#define m_SCL_DSP_FRAME_HST (0xfff<<0) -#define v_SCL_DSP_FRAME_VST(x) (((x)&0xfff)<<16) -#define v_SCL_DSP_FRAME_HST(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG3 -#define m_SCL_DSP_HS_END (0xff<<16) -#define m_SCL_DSP_HTOTAL (0xfff<<0) -#define v_SCL_DSP_HS_END(x) (((x)&0xff)<<16) -#define v_SCL_DSP_HTOTAL(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG4 -#define m_SCL_DSP_HACT_ST (0x3ff<<16) -#define m_SCL_DSP_HACT_END (0xfff<<0) -#define v_SCL_DSP_HACT_ST(x) (((x)&0x3ff)<<16) -#define v_SCL_DSP_HACT_END(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG5 -#define m_SCL_DSP_VS_END (0xff<<16) -#define m_SCL_DSP_VTOTAL (0xfff<<0) -#define v_SCL_DSP_VS_END(x) (((x)&0xff)<<16) -#define v_SCL_DSP_VTOTAL(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG6 -#define m_SCL_DSP_VACT_ST (0xff<<16) -#define m_SCL_DSP_VACT_END (0xfff<<0) -#define v_SCL_DSP_VACT_ST(x) (((x)&0xff)<<16) -#define v_SCL_DSP_VACT_END(x) (((x)&0xfff)<<0) - - -//LCDC_SCL_REG7 -#define m_SCL_DSP_HBOR_ST (0x3ff<<16) -#define m_SCL_DSP_HBOR_END (0xfff<<0) -#define v_SCL_DSP_HBOR_ST(x) (((x)&0x3ff)<<16) -#define v_SCL_DSP_HBOR_END(x) (((x)&0xfff)<<0) - -//LCDC_SCL_REG8 - -#define m_SCL_DSP_VBOR_ST (0xff<<16) -#define m_SCL_DSP_VBOR_END (0xfff<<0) -#define v_SCL_DSP_VBOR_ST(x) (((x)&0xff)<<16) -#define v_SCL_DSP_VBOR_END(x) (((x)&0xfff)<<0) - - - - - -#define CalScale(x, y) (((u32)(x)*0x1000)/(y)) -struct rk2928_lcdc_device{ - int id; - struct rk_lcdc_device_driver driver; - rk_screen *screen; - - LCDC_REG *preg; // LCDC reg base address and backup reg - LCDC_REG regbak; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - struct clk *sclk; //scale clk - struct clk *aclk_parent; //lcdc aclk divider frequency source - struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. - struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. - struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. - struct clk *pd_display; // display power domain - u32 pixclock; -}; - -struct lcdc_info{ -/*LCD CLK*/ - struct rk2928_lcdc_device lcdc0; - -}; - - -struct win_set { - volatile u32 y_offset; - volatile u32 c_offset; -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 c_offset; - u32 xpos; //size in panel - u32 ypos; - u32 xsize; //start point in panel - u32 ysize; - enum data_format format; - - wait_queue_head_t wait; - struct win_set mirror; - struct win_set displ; - struct win_set done; - - u8 par_seted; - u8 addr_seted; -}; - -#endif - - diff --git a/drivers/video/rockchip/chips/rk30_lcdc.c b/drivers/video/rockchip/chips/rk30_lcdc.c deleted file mode 100644 index 3c4bfb0975f6..000000000000 --- a/drivers/video/rockchip/chips/rk30_lcdc.c +++ /dev/null @@ -1,1245 +0,0 @@ -/* - * drivers/video/rockchip/chips/rk30_lcdc.c - * - * Copyright (C) 2012 ROCKCHIP, Inc. - *Author:yzq - * yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk30_lcdc.h" - - - - - - -static int dbg_thresd = 0; -module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); -#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) - - -static int rk30_lcdc_init(struct rk_lcdc_device_driver *dev_drv) -{ - int i = 0; - int __iomem *c; - int v; - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - if(lcdc_dev->id == 0) //lcdc0 - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); - } - else if(lcdc_dev->id == 1) - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); - } - else - { - printk(KERN_ERR "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) - { - printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); - } - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config - clk_enable(lcdc_dev->aclk); - lcdc_dev->clk_on = 1; - LcdMskReg(lcdc_dev,SYS_CTRL0,m_HWC_CHANNEL_ID | m_WIN2_CHANNEL_ID | m_WIN1_CBR_CHANNEL_ID | - m_WIN1_YRGB_CHANNEL_ID | m_WIN0_CBR_CHANNEL1_ID | m_WIN0_YRGB_CHANNEL1_ID | - m_WIN0_CBR_CHANNEL0_ID | m_WIN0_YRGB_CHANNEL0_ID,v_HWC_CHANNEL_ID(7) | - v_WIN2_CHANNEL_ID(6) | v_WIN1_CBR_CHANNEL_ID(5) | v_WIN1_YRGB_CHANNEL_ID(4) | - v_WIN0_CBR_CHANNEL1_ID(3) | v_WIN0_YRGB_CHANNEL1_ID(2) | v_WIN0_CBR_CHANNEL0_ID(1) | - v_WIN0_YRGB_CHANNEL0_ID(0)); //channel id ,just use default value - LcdSetBit(lcdc_dev,DSP_CTRL0, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | - m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | - v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync - if(dev_drv->cur_screen->dsp_lut) - { - LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - LCDC_REG_CFG_DONE(); - msleep(25); - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - } - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - return 0; -} - -static int rk30_lcdc_deinit(struct rk30_lcdc_device *lcdc_dev) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LcdMskReg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN | - m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) | - v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt - LcdSetBit(lcdc_dev,SYS_CTRL0,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - mdelay(1); - - return 0; -} - -static int rk30_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - rk_screen *screen = dev_drv->cur_screen; - u64 ft; - int fps; - u16 face; - u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; - u16 right_margin = screen->right_margin; - u16 lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - - // set the rgb or mcu - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(screen->type==SCREEN_MCU) - { - LcdMskReg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1)); - // set out format and mcu timing - mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; - if(mcu_total>31) - mcu_total = 31; - if(mcu_total<3) - mcu_total = 3; - mcu_rwstart = (mcu_total+1)/4 - 1; - mcu_rwend = ((mcu_total+1)*3)/4 - 1; - mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); - mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); - - //DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", - // mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); - - // set horizontal & vertical out timing - - right_margin = x_res/6; - screen->pixclock = 150000000; //mcu fix to 150 MHz - LcdMskReg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | - m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, - v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | - v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | - v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0)); - - } - - switch (screen->face) - { - case OUT_P565: - face = OUT_P565; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_P666: - face = OUT_P666; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_D888_P565: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_D888_P666: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_P888: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1)); - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - break; - default: - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - face = screen->face; - break; - } - - //use default overlay,set vsyn hsync den dclk polarity - LcdMskReg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | - m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) | - v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | - v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk)); - - //set background color to black,set swap according to the screen panel,disable blank mode - LcdMskReg(lcdc_dev, DSP_CTRL1, m_BG_COLOR | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | - m_DUMMY_SWAP | m_BLANK_MODE,v_BG_COLOR(0x000000) | v_OUTPUT_RB_SWAP(screen->swap_rb) | - v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy) | - v_BLACK_MODE(0)); - - - LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | - v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); - LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | - v_HASP(screen->hsync_len + screen->left_margin)); - - LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | - v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| - v_VASP(screen->vsync_len + screen->upper_margin)); - // let above to take effect - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - clk_enable(lcdc_dev->dclk); - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps; - printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps); - - if(screen->init) - { - screen->init(); - } - - printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); - return 0; -} - -static int mcu_refresh(struct rk30_lcdc_device *lcdc_dev) -{ - - return 0; -} - - - -//enable layer,open:1,enable;0 disable -static int win0_open(struct rk30_lcdc_device *lcdc_dev,bool open) -{ - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[0]->state = open; - - LcdMskReg(lcdc_dev, SYS_CTRL1, m_W0_EN, v_W0_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} -static int win1_open(struct rk30_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); - LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - LcdMskReg(lcdc_dev, SYS_CTRL1, m_W1_EN, v_W1_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); - LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} - -static int win2_open(struct rk30_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdMskReg(lcdc_dev, SYS_CTRL1, m_W2_EN, v_W2_EN(open)); - LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); - lcdc_dev->driver.layer_par[1]->state = open; - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win2 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} - -static int rk30_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) -{ - struct rk30_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk30_lcdc_device ,driver); - - printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0)); - break; - case FB_BLANK_NORMAL: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - default: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_YRGB_MST0, y_addr); - LcdWrReg(lcdc_dev, WIN0_CBR_MST0, uv_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN1_YRGB_MST, y_addr); - LcdWrReg(lcdc_dev, WIN1_CBR_MST, uv_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win2_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN2_MST, y_addr); - LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - - xact = par->xact; //active (origin) picture window width/height - yact = par->yact; - xvir = par->xvir; // virtual resolution - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - - ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor - ScaleYrgbY = CalScale(yact, par->ysize); - switch (par->format) - { - case YUV422:// yuv422 - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - break; - } - - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); - LcdMskReg(lcdc_dev, SYS_CTRL1, m_W0_FORMAT, v_W0_FORMAT(par->format)); //(inf->video_mode==0) - LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); - LcdMskReg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, - v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case ARGB888: - LcdWrReg(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - LcdWrReg(lcdc_dev, WIN0_VIR,v_RGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1)); - break; - case RGB565: //rgb565 - LcdWrReg(lcdc_dev, WIN0_VIR,v_RGB565_VIRWIDTH(xvir)); - break; - case YUV422: - case YUV420: - LcdWrReg(lcdc_dev, WIN0_VIR,v_YUV_VIRWIDTH(xvir)); - break; - default: - LcdWrReg(lcdc_dev, WIN0_VIR,v_RGB888_VIRWIDTH(xvir)); - break; - } - - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - ScaleYrgbX = CalScale(xact, par->xsize); - ScaleYrgbY = CalScale(yact, par->ysize); - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch (par->format) - { - case YUV422:// yuv422 - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - break; - } - - LcdWrReg(lcdc_dev, WIN1_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - LcdWrReg(lcdc_dev, WIN1_SCL_FACTOR_CBR, v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY)); - LcdMskReg(lcdc_dev,SYS_CTRL1, m_W1_FORMAT, v_W1_FORMAT(par->format)); - LcdWrReg(lcdc_dev, WIN1_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case ARGB888: - LcdWrReg(lcdc_dev, WIN1_VIR,v_ARGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - LcdWrReg(lcdc_dev, WIN1_VIR,v_RGB888_VIRWIDTH(xvir)); - // LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB565: //rgb565 - LcdWrReg(lcdc_dev, WIN1_VIR,v_RGB565_VIRWIDTH(xvir)); - break; - case YUV422: - case YUV420: - LcdWrReg(lcdc_dev, WIN1_VIR,v_YUV_VIRWIDTH(xvir)); - break; - default: - LcdWrReg(lcdc_dev, WIN1_VIR,v_RGB888_VIRWIDTH(xvir)); - break; - } - - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int win2_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - ScaleYrgbX = CalScale(xact, par->xsize); - ScaleYrgbY = CalScale(yact, par->ysize); - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - - LcdMskReg(lcdc_dev,SYS_CTRL1, m_W2_FORMAT, v_W2_FORMAT(par->format)); - LcdWrReg(lcdc_dev, WIN2_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN2_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(lcdc_dev, WIN2_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); - switch(par->format) - { - case ARGB888: - LcdWrReg(lcdc_dev, WIN2_VIR,v_ARGB888_VIRWIDTH(xvir)); - //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB888: //rgb888 - LcdWrReg(lcdc_dev, WIN2_VIR,v_RGB888_VIRWIDTH(xvir)); - // LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); - break; - case RGB565: //rgb565 - LcdWrReg(lcdc_dev, WIN2_VIR,v_RGB565_VIRWIDTH(xvir)); - break; - case YUV422: - case YUV420: - LcdWrReg(lcdc_dev, WIN2_VIR,v_YUV_VIRWIDTH(xvir)); - break; - default: - LcdWrReg(lcdc_dev, WIN2_VIR,v_RGB888_VIRWIDTH(xvir)); - break; - } - - LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk30_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - if(layer_id == 0) - { - win0_open(lcdc_dev,open); - } - else if(layer_id == 1) - { - win1_open(lcdc_dev,open); - } - else if(layer_id == 2) - { - win2_open(lcdc_dev,open); - } - - return 0; -} - -static int rk30_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_set_par(lcdc_dev,screen,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_set_par(lcdc_dev,screen,par); - } - else if(layer_id == 2) - { - par = dev_drv->layer_par[2]; - win2_set_par(lcdc_dev,screen,par); - } - - return 0; -} - -int rk30_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - unsigned long flags; - int timeout; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_display(lcdc_dev,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_display(lcdc_dev,par); - } - else if(layer_id == 2) - { - par = dev_drv->layer_par[2]; - win2_display(lcdc_dev,par); - } - if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt - { - dev_drv->first_frame = 0; - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN , - v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1)); - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - - } - - if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn - { - spin_lock_irqsave(&dev_drv->cpl_lock,flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); - if(!timeout&&(!dev_drv->frame_done.done)) - { - printk(KERN_ERR "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -int rk30_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - int ret = 0; - switch(cmd) - { - case FBIOGET_PANEL_SIZE: //get panel size - panel_size[0] = dev_drv->screen0->x_res; - panel_size[1] = dev_drv->screen0->y_res; - if(copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - default: - break; - } - - return ret; -} -static int rk30_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - struct layer_par *par = dev_drv->layer_par[layer_id]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(layer_id == 0) - { - par->state = LcdReadBit(lcdc_dev,SYS_CTRL1,m_W0_EN); - } - else if( layer_id == 1) - { - par->state = LcdReadBit(lcdc_dev,SYS_CTRL1,m_W1_EN); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return par->state; - -} - -/*********************************** -overlay manager -swap:1 win0 on the top of win1 - 0 win1 on the top of win0 -set : 1 set overlay - 0 get overlay state -************************************/ -static int rk30_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(set) //set overlay - { - LcdMskReg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); - LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); - LCDC_REG_CFG_DONE(); - ovl = swap; - } - else //get overlay - { - ovl = LcdReadBit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); - } - } - else - { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} -static int rk30_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - return 0; -} - - -/******************************************* -lcdc fps manager,set or get lcdc fps -set:0 get - 1 set -********************************************/ -static int rk30_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - rk_screen * screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - - if(set) - { - ft = div_u64(1000000000000llu,fps); - dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); - dotclk = div_u64(1000000000000llu,dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - } - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps ; //one frame time in ms - return fps; -} - -static int rk30_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if(order == FB_DEFAULT_ORDER ) - { - order = FB0_WIN1_FB1_WIN0_FB2_WIN2; - } - dev_drv->fb2_win_id = order/100; - dev_drv->fb1_win_id = (order/10)%10; - dev_drv->fb0_win_id = order%10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, - dev_drv->fb2_win_id); - - return 0; -} - -static int rk30_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) -{ - int layer_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if(!strcmp(id,"fb0")||!strcmp(id,"fb3")) - { - layer_id = dev_drv->fb0_win_id; - } - else if(!strcmp(id,"fb1")||!strcmp(id,"fb4")) - { - layer_id = dev_drv->fb1_win_id; - } - else if(!strcmp(id,"fb2")||!strcmp(id,"fb5")) - { - layer_id = dev_drv->fb2_win_id; - } - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return layer_id; -} - -static int rk30_read_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) -{ - - return 0; -} - -static int rk30_set_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) -{ - int i=0; - int __iomem *c; - int v; - int ret = 0; - - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - LCDC_REG_CFG_DONE(); - msleep(25); - if(dev_drv->cur_screen->dsp_lut) - { - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - } - else - { - printk(KERN_WARNING "no buffer to backup lut data!\n"); - ret = -1; - } - LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - LCDC_REG_CFG_DONE(); - - return ret; -} -int rk30_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - - mdelay(1); - clk_disable(lcdc_dev->dclk); - clk_disable(lcdc_dev->hclk); - clk_disable(lcdc_dev->aclk); - clk_disable(lcdc_dev->pd); - - return 0; -} - - -int rk30_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); - int i=0; - int __iomem *c; - int v; - if(!lcdc_dev->clk_on) - { - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); - clk_enable(lcdc_dev->dclk); - clk_enable(lcdc_dev->aclk); - } - memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg - - spin_lock(&lcdc_dev->reg_lock); - if(dev_drv->cur_screen->dsp_lut) //resume dsp lut - { - LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); - LCDC_REG_CFG_DONE(); - mdelay(25); - for(i=0;i<256;i++) - { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base+i; - writel_relaxed(v,c); - - } - LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); - } - if(lcdc_dev->atv_layer_cnt) - { - LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - LCDC_REG_CFG_DONE(); - } - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} -static irqreturn_t rk30_lcdc_isr(int irq, void *dev_id) -{ - struct rk30_lcdc_device *lcdc_dev = (struct rk30_lcdc_device *)dev_id; - - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); - LCDC_REG_CFG_DONE(); - //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); - - if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync - { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - return IRQ_HANDLED; -} - -static struct layer_par lcdc_layer[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, - [2] = { - .name = "win2", - .id = 2, - .support_3d = false, - }, -}; - -static struct rk_lcdc_device_driver lcdc_driver = { - .name = "lcdc", - .def_layer_par = lcdc_layer, - .num_layer = ARRAY_SIZE(lcdc_layer), - .open = rk30_lcdc_open, - .init_lcdc = rk30_lcdc_init, - .ioctl = rk30_lcdc_ioctl, - .suspend = rk30_lcdc_early_suspend, - .resume = rk30_lcdc_early_resume, - .set_par = rk30_lcdc_set_par, - .blank = rk30_lcdc_blank, - .pan_display = rk30_lcdc_pan_display, - .load_screen = rk30_load_screen, - .get_layer_state = rk30_lcdc_get_layer_state, - .ovl_mgr = rk30_lcdc_ovl_mgr, - .get_disp_info = rk30_lcdc_get_disp_info, - .fps_mgr = rk30_lcdc_fps_mgr, - .fb_get_layer = rk30_fb_get_layer, - .fb_layer_remap = rk30_fb_layer_remap, - .set_dsp_lut = rk30_set_dsp_lut, - .read_dsp_lut = rk30_read_dsp_lut, -}; -#ifdef CONFIG_PM -static int rk30_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk30_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} - -#else -#define rk30_lcdc_suspend NULL -#define rk30_lcdc_resume NULL -#endif - -static int __devinit rk30_lcdc_probe (struct platform_device *pdev) -{ - struct rk30_lcdc_device *lcdc_dev=NULL; - rk_screen *screen; - struct rk29fb_info *screen_ctr_info; - struct resource *res = NULL; - struct resource *mem; - int ret = 0; - - /*************Malloc rk30lcdc_inf and set it to pdev for drvdata**********/ - lcdc_dev = kzalloc(sizeof(struct rk30_lcdc_device), GFP_KERNEL); - if(!lcdc_dev) - { - dev_err(&pdev->dev, ">>rk30 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->id = pdev->id; - screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; - screen = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen) - { - dev_err(&pdev->dev, ">>rk30 lcdc screen kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - /****************get lcdc0 reg *************************/ - res = platform_get_resource(pdev, IORESOURCE_MEM,0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); - if (lcdc_dev->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "cannot map IO\n"); - ret = -ENXIO; - goto err2; - } - - lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; - lcdc_dev->dsp_lut_addr_base = &lcdc_dev->preg->DSP_LUT_ADDR; - printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); - lcdc_dev->driver.dev=&pdev->dev; - lcdc_dev->driver.screen0 = screen; - lcdc_dev->driver.cur_screen = screen; - lcdc_dev->driver.screen_ctr_info = screen_ctr_info; - spin_lock_init(&lcdc_dev->reg_lock); - lcdc_dev->irq = platform_get_irq(pdev, 0); - if(lcdc_dev->irq < 0) - { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err3; - } - ret = request_irq(lcdc_dev->irq, rk30_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); - if (ret) - { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); - ret = -EBUSY; - goto err3; - } - ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); - if(ret < 0) - { - printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); - goto err4; - } - printk("rk30 lcdc%d probe ok!\n",lcdc_dev->id); - - return 0; - -err4: - free_irq(lcdc_dev->irq,lcdc_dev); -err3: - iounmap(lcdc_dev->reg_vir_base); -err2: - release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); -err1: - kfree(screen); -err0: - platform_set_drvdata(pdev, NULL); - kfree(lcdc_dev); - return ret; - -} -static int __devexit rk30_lcdc_remove(struct platform_device *pdev) -{ - struct rk30_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk_fb_unregister(&(lcdc_dev->driver)); - rk30_lcdc_deinit(lcdc_dev); - iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev); - return 0; -} - -static void rk30_lcdc_shutdown(struct platform_device *pdev) -{ - struct rk30_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary - lcdc_dev->driver.cur_screen->standby(1); - if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary - lcdc_dev->driver.screen_ctr_info->io_disable(); - if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds if necessary - lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); - rk_fb_unregister(&(lcdc_dev->driver)); - rk30_lcdc_deinit(lcdc_dev); - /*iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev);*/ -} - - -static struct platform_driver rk30lcdc_driver = { - .probe = rk30_lcdc_probe, - .remove = __devexit_p(rk30_lcdc_remove), - .driver = { - .name = "rk30-lcdc", - .owner = THIS_MODULE, - }, - .suspend = rk30_lcdc_suspend, - .resume = rk30_lcdc_resume, - .shutdown = rk30_lcdc_shutdown, -}; - -static int __init rk30_lcdc_module_init(void) -{ - return platform_driver_register(&rk30lcdc_driver); -} - -static void __exit rk30_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk30lcdc_driver); -} - - - -fs_initcall(rk30_lcdc_module_init); -module_exit(rk30_lcdc_module_exit); - - - diff --git a/drivers/video/rockchip/chips/rk30_lcdc.h b/drivers/video/rockchip/chips/rk30_lcdc.h deleted file mode 100644 index 9576ed54c59a..000000000000 --- a/drivers/video/rockchip/chips/rk30_lcdc.h +++ /dev/null @@ -1,542 +0,0 @@ -#ifndef RK30_LCDC_H_ -#define RK30_LCDC_H_ - -#include - -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) -#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ - -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CTRL0; //0x00 system control register 0 - unsigned int SYS_CTRL1; //0x04 system control register 1 - unsigned int DSP_CTRL0; //0x08 display control register 0 - unsigned int DSP_CTRL1; //0x0c display control register 1 - unsigned int INT_STATUS; //0x10 Interrupt status register - unsigned int MCU_CTRL ; //0x14 MCU mode contol register - unsigned int BLEND_CTRL; //0x18 Blending control register - unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register - unsigned int WIN2_COLOR_KEY_CTRL; //0x24 Win2 blending control register - unsigned int WIN0_YRGB_MST0; //0x28 Win0 active YRGB memory start address0 - unsigned int WIN0_CBR_MST0; //0x2c Win0 active Cbr memory start address0 - unsigned int WIN0_YRGB_MST1; //0x30 Win0 active YRGB memory start address1 - unsigned int WIN0_CBR_MST1; //0x34 Win0 active Cbr memory start address1 - unsigned int WIN0_VIR; //0x38 WIN0 virtual display width/height - unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height - unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel - unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel - unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting - unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset - unsigned int WIN1_YRGB_MST; //0x54 Win1 active YRGB memory start address - unsigned int WIN1_CBR_MST; //0x58 Win1 active Cbr memory start address - unsigned int WIN1_VIR; //0x5c WIN1 virtual display width/height - unsigned int WIN1_ACT_INFO; //0x60 Win1 active window width/height - unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel - unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel - unsigned int WIN1_SCL_FACTOR_YRGB; //0x6c Win1 YRGB scaling factor setting - unsigned int WIN1_SCL_FACTOR_CBR; //0x70 Win1 YRGB scaling factor setting - unsigned int WIN1_SCL_OFFSET; //0x74 Win1 Cbr scaling start point offset - unsigned int WIN2_MST; //0x78 win2 memort start address - unsigned int WIN2_VIR; //0x7c win2 virtual stride - unsigned int WIN2_DSP_INFO; //0x80 Win2 display width/height on panel - unsigned int WIN2_DSP_ST; //0x84 Win2 display start point on panel - unsigned int HWC_MST; //0x88 HWC memory start address - unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point - unsigned int DSP_VS_ST_END_F1; //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode - unsigned int DSP_VACT_ST_END_F1; //0xb0 Vertical scanning active start/end point of even filed in interlace mode - unsigned int reserved0[(0xc0-0xb4)/4]; - unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH - unsigned int reserved1[(0x100-0xc4)/4]; - unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port - unsigned int reserved2[(0x200-0x104)/4]; - unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port - unsigned int reserved3[(0x400-0x204)/4]; - unsigned int WIN2_LUT_ADDR; - unsigned int reserved4[(0x800-0x404)/4]; - unsigned int DSP_LUT_ADDR; - -} LCDC_REG, *pLCDC_REG; - - -/* SYS_CONFIG */ - -#define m_LCDC_DMA_STOP (1<<0) -#define m_LCDC_STANDBY (1<<1) -#define m_HWC_RELOAD_EN (1<<2) -#define m_W0_AXI_OUTSTANDING_DISABLE (1<<3) -#define m_W1_AXI_OUTSTANDING_DISABLE (1<<4) -#define m_W2_AXI_OUTSTANDING_DISABLE (1<<5) -#define m_DMA_BURST_LENGTH (3<<6) -#define m_WIN0_YRGB_CHANNEL0_ID ((0x07)<<8) -#define m_WIN0_CBR_CHANNEL0_ID ((0x07)<<11) -#define m_WIN0_YRGB_CHANNEL1_ID ((0x07)<<14) -#define m_WIN0_CBR_CHANNEL1_ID ((0x07)<<17) -#define m_WIN1_YRGB_CHANNEL_ID ((0x07)<<20) -#define m_WIN1_CBR_CHANNEL_ID ((0x07)<<23) -#define m_WIN2_CHANNEL_ID ((0x07)<<26) -#define m_HWC_CHANNEL_ID ((0x07)<<29) - - - - - -#define v_LCDC_DMA_STOP(x) (((x)&1)<<0) -#define v_LCDC_STANDBY(x) (((x)&1)<<1) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<2) -#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3) -#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4) -#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6) -#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8) -#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11) -#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14) -#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17) -#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20) -#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23) -#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26) -#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29) - - - -//LCDC_SYS_CTRL1 -#define m_W0_EN (1<<0) -#define m_W1_EN (1<<1) -#define m_W2_EN (1<<2) -#define m_HWC_EN (1<<3) -#define m_W0_FORMAT (7<<4) -#define m_W1_FORMAT (7<<7) -#define m_W2_FORMAT (7<<10) -#define m_HWC_COLOR_MODE (1<<13) -#define m_HWC_SIZE_SELET (1<<14) -#define m_W0_3D_MODE_EN (1<<15) -#define m_W0_3D_MODE_SELET (7<<16) -#define m_W0_RGB_RB_SWAP (1<<19) -#define m_W0_RGB_ALPHA_SWAP (1<<20) -#define m_W0_YRGB_M8_SWAP (1<<21) -#define m_W0_CBCR_SWAP (1<<22) -#define m_W1_RGB_RB_SWAP (1<<23) -#define m_W1_RGB_ALPHA_SWAP (1<<24) -#define m_W1_YRGB_M8_SWAP (1<<25) -#define m_W1_CBCR_SWAP (1<<26) -#define m_W2_RGB_RB_SWAP (1<<27) -#define m_W2_RGB_ALPHA_SWAP (1<<28) -#define m_W2_8pp_PALETTE_ENDIAN_SELECT (1<<29) -#define m_W2_LUT_RAM_EN (1<<30) -#define m_DSP_LUT_RAM_EN (1<<31) - -#define v_W0_EN(x) (((x)&1)<<0) -#define v_W1_EN(x) (((x)&1)<<1) -#define v_W2_EN(x) (((x)&1)<<2) -#define v_HWC_EN(x) (((x)&1)<<3) -#define v_W0_FORMAT(x) (((x)&7)<<4) -#define v_W1_FORMAT(x) (((x)&7)<<7) -#define v_W2_FORMAT(x) (((x)&7)<<10) -#define v_HWC_COLOR_MODE(x) (((x)&1)<<13) -#define v_HWC_SIZE_SELET(x) (((x)&1)<<14) -#define v_W0_3D_MODE_EN(x) (((x)&1)<<15) -#define v_W0_3D_MODE_SELET(x) (((x)&3)<<16) -#define v_W0_RGB_RB_SWAP(x) (((x)&1)<<19) -#define v_W0_RGB_ALPHA_SWAP(x) (((x)&1)<<20) -#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<21) -#define v_W0_CBCR_SWAP(x) (((x)&1)<<22) -#define v_W1_RGB_RB_SWAP(x) (((x)&1)<<23) -#define v_W1_RGB_ALPHA_SWAP(x) (((x)&1)<<24) -#define v_W1_YRGB_M8_SWAP(x) (((x)&1)<<25) -#define v_W1_CBCR_SWAP(x) (((x)&1)<<26) -#define v_W2_RGB_RB_SWAP(x) (((x)&1)<<27) -#define v_W2_RGB_ALPHA_SWAP(x) (((x)&1)<<28) -#define v_W2_8pp_PALETTE_ENDIAN_SELECT (((x)&1)<<29) -#define v_W2_LUT_RAM_EN(x) (((x)&1)<<30) -#define v_DSP_LUT_RAM_EN(x) (((x)&1)<<31) - -//LCDC_DSP_CTRL_REG0 -#define m_DISPLAY_FORMAT (0x0f<<0) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_W0W1_POSITION_SWAP (1<<8) -#define m_DITHER_UP_EN (1<<9) -#define m_DITHER_DOWN_MODE (1<<10) -#define m_DITHER_DOWN_EN (1<<11) -#define m_INTERLACE_DSP_EN (1<<12) -#define m_INTERLACE_FIELD_POLARITY (1<<13) -#define m_W0_INTERLACE_READ_MODE (1<<14) -#define m_W1_INTERLACE_READ_MODE (1<<15) -#define m_W2_INTERLACE_READ_MODE (1<<16) -#define m_W0_YRGB_DEFLICK_MODE (1<<17) -#define m_W0_CBR_DEFLICK_MODE (1<<18) -#define m_W1_YRGB_DEFLICK_MODE (1<<19) -#define m_W1_CBR_DEFLICK_MODE (1<<20) -#define m_W0_ALPHA_MODE (1<<21) -#define m_W1_ALPHA_MODE (1<<22) -#define m_W2_ALPHA_MODE (1<<23) -#define m_W0_COLOR_SPACE_CONVERSION (3<<24) -#define m_W1_COLOR_SPACE_CONVERSION (3<<26) -#define m_W2_COLOR_SPACE_CONVERSION (1<<28) -#define m_YCRCB_CLIP_EN (1<<29) -#define m_CBR_FILTER_656 (1<<30) -#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) //eanble for low power - -#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8) -#define v_DITHER_UP_EN(x) (((x)&1)<<9) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<11) -#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) -#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14) -#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15) -#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16) -#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17) -#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18) -#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19) -#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20) -#define v_W0_ALPHA_MODE(x) (((x)&1)<<21) -#define v_W1_ALPHA_MODE(x) (((x)&1)<<22) -#define v_W2_ALPHA_MODE(x) (((x)&1)<<23) -#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24) -#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26) -#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28) -#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29) -#define v_CBR_FILTER_656(x) (((x)&1)<<30) -#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) //eanble for low power - -//LCDC_DSP_CTRL_REG1 -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define m_BLANK_MODE (1<<24) -#define m_BLACK_MODE (1<<25) -#define m_OUTPUT_BG_SWAP (1<<26) -#define m_OUTPUT_RB_SWAP (1<<27) -#define m_OUTPUT_RG_SWAP (1<<28) -#define m_DELTA_SWAP (1<<29) -#define m_DUMMY_SWAP (1<<30) - -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) -#define v_BLANK_MODE(x) (((x)&1)<<24) -#define v_BLACK_MODE(x) (((x)&1)<<25) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<26) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<27) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<28) -#define v_DELTA_SWAP(x) (((x)&1)<<29) -#define v_DUMMY_SWAP(x) (((x)&1)<<30) - - -//LCDC_INT_STATUS -#define v_HOR_START_INT_STA (1<<0) //status -#define v_FRM_START_INT_STA (1<<1) -#define v_LINE_FLAG_INT_STA (1<<2) -#define v_BUS_ERR_INT_STA (1<<3) -#define m_HOR_START_INT_EN (1<<4) //enable -#define m_FRM_START_INT_EN (1<<5) -#define m_LINE_FLAG_INT_EN (1<<6) -#define m_BUS_ERR_INT_EN (1<<7) -#define m_HOR_START_INT_CLEAR (1<<8) //auto clear -#define m_FRM_START_INT_CLEAR (1<<9) -#define m_LINE_FLAG_INT_CLEAR (1<<10) -#define m_BUS_ERR_INT_CLEAR (1<<11) -#define m_LINE_FLAG_NUM (0xfff<<12) -#define v_HOR_START_INT_EN(x) (((x)&1)<<4) -#define v_FRM_START_INT_EN(x) (((x)&1)<<5) -#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6) -#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) -#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8) -#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9) -#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10) -#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) -#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) - - - -//LCDC_MCU_TIMING_CTRL -#define m_MCU_WRITE_PERIOD (0x3f<<0) -#define m_MCU_CS_ST (0xf<<6) -#define m_MCU_CS_END (0x3f<<10) -#define m_MCU_RW_ST (0xf<<16) -#define m_MCU_RW_END (0x3f<<20) -#define m_MCU_BPS_CLK_SEL (1<<26) -#define m_MCU_HOLDMODE_SELECT (1<<27) -#define m_MCU_HOLDMODE_FRAME_ST (1<<28) -#define m_MCU_RS_SELECT (1<<29) -#define m_MCU_BYPASSMODE_SELECT (1<<30) -#define m_MCU_OUTPUT_SELECT (1<<31) -#define v_MCU_WRITE_PERIOD(x) (((x)&0x3f)<<0) -#define v_MCU_CS_ST(x) (((x)&0xf)<<6) -#define v_MCU_CS_END(x) (((x)&0x3f)<<10) -#define v_MCU_RW_ST(x) (((x)&0xf)<<16) -#define v_MCU_RW_END(x) (((x)&0x3f)<<20) -#define v_MCU_BPS_CLK_SEL (((x)&1)<<26) -#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) -#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS_SELECT(x) (((x)&1)<<29) -#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) -#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) - -//LCDC_ BLEND_CTRL -#define m_HWC_BLEND_EN (1<<0) -#define m_W2_BLEND_EN (1<<1) -#define m_W1_BLEND_EN (1<<2) -#define m_W0_BLEND_EN (1<<3) -#define m_HWC_BLEND_FACTOR (15<<4) -#define m_W2_BLEND_FACTOR (0xff<<8) -#define m_W1_BLEND_FACTOR (0xff<<16) -#define m_W0_BLEND_FACTOR (0xff<<24) - -#define v_HWC_BLEND_EN(x) (((x)&1)<<0) -#define v_W2_BLEND_EN(x) (((x)&1)<<1) -#define v_W1_BLEND_EN(x) (((x)&1)<<2) -#define v_W0_BLEND_EN(x) (((x)&1)<<3) -#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) -#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) - - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - - - - - -//AXI MS ID -#define m_W0_YRGB_CH_ID (0xF<<0) -#define m_W0_CBR_CH_ID (0xF<<4) -#define m_W1_YRGB_CH_ID (0xF<<8) -#define m_W2_CH_ID (0xF<<12) -#define m_HWC_CH_ID (0xF<<16) -#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) -#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) -#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) -#define v_W2_CH_ID(x) (((x)&0xF)<<12) -#define v_HWC_CH_ID(x) (((x)&0xF)<<16) - - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - - -//LCDC_WINx_SCL_FACTOR_Y/CBCR -#define v_X_SCL_FACTOR(x) ((x)<<0) -#define v_Y_SCL_FACTOR(x) ((x)<<16) - -//LCDC_DSP_HTOTAL_HS_END -#define v_HSYNC(x) ((x)<<0) //hsync pulse width -#define v_HORPRD(x) ((x)<<16) //horizontal period - - -//LCDC_DSP_HACT_ST_END -#define v_HAEP(x) ((x)<<0) //horizontal active end point -#define v_HASP(x) ((x)<<16) //horizontal active start point - -//LCDC_DSP_VTOTAL_VS_END -#define v_VSYNC(x) ((x)<<0) -#define v_VERPRD(x) ((x)<<16) - -//LCDC_DSP_VACT_ST_END -#define v_VAEP(x) ((x)<<0) -#define v_VASP(x) ((x)<<16) - - -//LCDC_WINx_VIR ,x is number of words of win0 virtual width -#define v_ARGB888_VIRWIDTH(x) (x) -#define v_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3)) -#define v_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0)) -#define v_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0)) - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_WIN0_ACT_INFO -#define v_ACT_WIDTH(x) ((x-1)<<0) -#define v_ACT_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_INFO -#define v_DSP_WIDTH(x) ((x-1)<<0) -#define v_DSP_HEIGHT(x) ((x-1)<<16) - -//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning -#define v_DSP_STX(x) (x<<0) -#define v_DSP_STY(x) (x<<16) - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - - -#define CalScale(x, y) (((u32)x*0x1000)/y) -struct rk30_lcdc_device{ - int id; - struct rk_lcdc_device_driver driver; - rk_screen *screen; - - LCDC_REG *preg; // LCDC reg base address and backup reg - LCDC_REG regbak; - int __iomem *dsp_lut_addr_base; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - struct clk *aclk_parent; //lcdc aclk divider frequency source - struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. - struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. - struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. - struct clk *pd_display; // display power domain - u32 pixclock; -}; - -struct lcdc_info{ -/*LCD CLK*/ - struct rk30_lcdc_device lcdc0; - struct rk30_lcdc_device lcdc1; - -}; - - -struct win_set { - volatile u32 y_offset; - volatile u32 c_offset; -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 c_offset; - u32 xpos; //size in panel - u32 ypos; - u32 xsize; //start point in panel - u32 ysize; - enum data_format format; - - wait_queue_head_t wait; - struct win_set mirror; - struct win_set displ; - struct win_set done; - - u8 par_seted; - u8 addr_seted; -}; - -#endif - - diff --git a/drivers/video/rockchip/chips/rk31_lcdc.c b/drivers/video/rockchip/chips/rk31_lcdc.c deleted file mode 100644 index 251e74913766..000000000000 --- a/drivers/video/rockchip/chips/rk31_lcdc.c +++ /dev/null @@ -1,1055 +0,0 @@ -/* - * drivers/video/rockchip/chips/rk31_lcdc.c - * - * Copyright (C) 2012 ROCKCHIP, Inc. - *Author:yzq - * yxj - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk31_lcdc.h" - - - - - - -static int dbg_thresd = 0; -module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); -#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) - - -static int init_rk31_lcdc(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - if(lcdc_dev->id == 0) //lcdc0 - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); - } - else if(lcdc_dev->id == 1) - { - lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); - lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); - lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); - lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); - } - else - { - printk(KERN_ERR "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) - { - printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); - } - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config - clk_enable(lcdc_dev->aclk); - lcdc_dev->clk_on = 1; - - LcdMskReg(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE | m_W0_AXI_OUTSTANDING2 | - m_W1_AXI_OUTSTANDING2,v_LCDC_AXICLK_AUTO_ENABLE(1) | v_W0_AXI_OUTSTANDING2(1) | - v_W1_AXI_OUTSTANDING2(1));//eanble axi-clk auto gating for low power - LcdWrReg(lcdc_dev,AXI_MS_ID,v_HWC_CHANNEL_ID(5) | v_WIN2_CHANNEL_ID(4) | - v_WIN1_YRGB_CHANNEL_ID(3) | v_WIN0_CBR_CHANNEL_ID(2) | - v_WIN0_YRGB_CHANNEL_ID(1)); - LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | - m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | - v_SCANNING_MASK(1)); //mask all interrupt in init - LcdMskReg(lcdc_dev,FIFO_WATER_MARK,m_WIN1_FIFO_FULL_LEVEL,v_WIN1_FIFO_FULL_LEVEL(0x1e0)); - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - return 0; -} - -static int rk31_lcdc_deinit(struct rk31_lcdc_device *lcdc_dev) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | - m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | - v_SCANNING_MASK(1)); //mask all interrupt in init - LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - mdelay(1); - - return 0; -} - -static int rk31_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - rk_screen *screen = dev_drv->cur_screen; - u64 ft; - int fps; - u16 face; - u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; - u16 right_margin = screen->right_margin; - u16 lower_margin = screen->lower_margin; - u16 x_res = screen->x_res, y_res = screen->y_res; - - // set the rgb or mcu - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(screen->type==SCREEN_MCU) - { - LcdMskReg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1)); - // set out format and mcu timing - mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; - if(mcu_total>31) - mcu_total = 31; - if(mcu_total<3) - mcu_total = 3; - mcu_rwstart = (mcu_total+1)/4 - 1; - mcu_rwend = ((mcu_total+1)*3)/4 - 1; - mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); - mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); - - //DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", - // mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); - - // set horizontal & vertical out timing - - right_margin = x_res/6; - screen->pixclock = 150000000; //mcu fix to 150 MHz - LcdMskReg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | - m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, - v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | - v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | - v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0)); - - } - - switch (screen->face) - { - case OUT_P565: - face = OUT_P565; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_P666: - face = OUT_P666; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_D888_P565: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); - break; - case OUT_D888_P666: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); - break; - case OUT_P888: - face = OUT_P888; - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1)); - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - break; - default: - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); - LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); - face = screen->face; - break; - } - - //use default overlay,set vsyn hsync den dclk polarity - LcdMskReg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | - m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) | - v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | - v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk)); - - //set background color to black,set swap according to the screen panel,disable blank mode - LcdMskReg(lcdc_dev, DSP_CTRL1, m_BG_COLOR | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | - m_DUMMY_SWAP | m_BLANK_MODE,v_BG_COLOR(0x000000) | v_OUTPUT_RB_SWAP(screen->swap_rb) | - v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy) | - v_BLACK_MODE(0)); - - - LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | - v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); - LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | - v_HASP(screen->hsync_len + screen->left_margin)); - - LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | - v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); - LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| - v_VASP(screen->vsync_len + screen->upper_margin)); - // let above to take effect - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - clk_enable(lcdc_dev->dclk); - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps; - printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps); - - if(screen->init) - { - screen->init(); - } - if(screen->sscreen_set) - { - screen->sscreen_set(screen,!initscreen); - } - printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); - return 0; -} - -static int mcu_refresh(struct rk31_lcdc_device *lcdc_dev) -{ - - return 0; -} - - - -//enable layer,open:1,enable;0 disable -static int win0_open(struct rk31_lcdc_device *lcdc_dev,bool open) -{ - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[0]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} -static int win1_open(struct rk31_lcdc_device *lcdc_dev,bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - if(open) - { - if(!lcdc_dev->atv_layer_cnt) - { - printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - } - lcdc_dev->atv_layer_cnt++; - } - else - { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.layer_par[1]->state = open; - - LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open)); - if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc - { - printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); - return 0; -} - - -static int rk31_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) -{ - struct rk31_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk31_lcdc_device ,driver); - - printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch(blank_mode) - { - case FB_BLANK_UNBLANK: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0)); - break; - case FB_BLANK_NORMAL: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - default: - LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); - break; - } - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_display(struct rk31_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr); - LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct rk31_lcdc_device *lcdc_dev,struct layer_par *par ) -{ - u32 y_addr; - u32 uv_addr; - y_addr = par->smem_start + par->y_offset; - uv_addr = par->cbr_start + par->c_offset; - DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN1_YRGB_MST, y_addr); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win0_set_par(struct rk31_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg =0 ; //data format register config value - - xact = par->xact; //active (origin) picture window width/height - yact = par->yact; - xvir = par->xvir; // virtual resolution - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - - ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor - ScaleYrgbY = CalScale(yact, par->ysize); - switch (par->format) - { - case ARGB888: - fmt_cfg = 0; - break; - case RGB565: - fmt_cfg = 1; - break; - case YUV422:// yuv422 - fmt_cfg = 2; - ScaleCbrX = CalScale((xact/2), par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - case YUV420: // yuv420 - fmt_cfg = 3; - ScaleCbrX = CalScale(xact/2, par->xsize); - ScaleCbrY = CalScale(yact/2, par->ysize); - break; - case YUV444:// yuv444 - fmt_cfg = 4; - ScaleCbrX = CalScale(xact, par->xsize); - ScaleCbrY = CalScale(yact, par->ysize); - break; - default: - break; - } - - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); - LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); - LcdMskReg(lcdc_dev,SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(fmt_cfg)); //(inf->video_mode==0) - LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); - LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); - LcdMskReg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, - v_COLORKEY_EN(0) | v_KEYCOLOR(0)); - LcdWrReg(lcdc_dev,WIN0_VIR,v_VIRWIDTH(xvir)); - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_set_par(struct rk31_lcdc_device *lcdc_dev,rk_screen *screen, - struct layer_par *par ) -{ - u32 xact, yact, xvir, yvir, xpos, ypos; - u32 ScaleYrgbX = 0x1000; - u32 ScaleYrgbY = 0x1000; - u32 ScaleCbrX = 0x1000; - u32 ScaleCbrY = 0x1000; - u8 fmt_cfg; - - xact = par->xact; - yact = par->yact; - xvir = par->xvir; - yvir = par->yvir; - xpos = par->xpos+screen->left_margin + screen->hsync_len; - ypos = par->ypos+screen->upper_margin + screen->vsync_len; - - ScaleYrgbX = CalScale(xact, par->xsize); - ScaleYrgbY = CalScale(yact, par->ysize); - DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", - __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); - - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - switch (par->format) - { - case ARGB888: - fmt_cfg = 0; - break; - case RGB565: - fmt_cfg = 1; - break; - default: - break; - } - - LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(fmt_cfg)); - LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); - LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); - // enable win1 color key and set the color to black(rgb=0) - LcdMskReg(lcdc_dev,WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(0) | v_KEYCOLOR(0)); - LcdWrReg(lcdc_dev,WIN1_VIR,v_VIRWIDTH(xvir)); - - LCDC_REG_CFG_DONE(); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int rk31_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - if(layer_id == 0) - { - win0_open(lcdc_dev,open); - } - else if(layer_id == 1) - { - win1_open(lcdc_dev,open); - } - - return 0; -} - -static int rk31_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_set_par(lcdc_dev,screen,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_set_par(lcdc_dev,screen,par); - } - - return 0; -} - -int rk31_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - struct layer_par *par = NULL; - rk_screen *screen = dev_drv->cur_screen; - unsigned long flags; - int timeout; - if(!screen) - { - printk(KERN_ERR "screen is null!\n"); - return -ENOENT; - } - if(layer_id==0) - { - par = dev_drv->layer_par[0]; - win0_display(lcdc_dev,par); - } - else if(layer_id==1) - { - par = dev_drv->layer_par[1]; - win1_display(lcdc_dev,par); - } - if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt - { - dev_drv->first_frame = 0; - LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_STARTCLEAR | m_FRM_STARTMASK , - v_FRM_STARTCLEAR(1) | v_FRM_STARTMASK(0)); - LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective - - } - - if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn - { - spin_lock_irqsave(&dev_drv->cpl_lock,flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); - if(!timeout&&(!dev_drv->frame_done.done)) - { - printk(KERN_ERR "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - -int rk31_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - int ret = 0; - switch(cmd) - { - case FBIOGET_PANEL_SIZE: //get panel size - panel_size[0] = lcdc_dev->screen->x_res; - panel_size[1] = lcdc_dev->screen->y_res; - if(copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - default: - break; - } - - return ret; -} -static int rk31_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - struct layer_par *par = dev_drv->layer_par[layer_id]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(layer_id == 0) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN); - } - else if( layer_id == 1) - { - par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN); - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return par->state; - -} - -/*********************************** -overlay manager -swap:1 win0 on the top of win1 - 0 win1 on the top of win0 -set : 1 set overlay - 0 get overlay state -************************************/ -static int rk31_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - int ovl; - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on) - { - if(set) //set overlay - { - LcdMskReg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); - LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); - LCDC_REG_CFG_DONE(); - ovl = swap; - } - else //get overlay - { - ovl = LcdReadBit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); - } - } - else - { - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} -static int rk31_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - return 0; -} - - -/******************************************* -lcdc fps manager,set or get lcdc fps -set:0 get - 1 set -********************************************/ -static int rk31_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - rk_screen * screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - - if(set) - { - ft = div_u64(1000000000000llu,fps); - dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); - dotclk = div_u64(1000000000000llu,dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - if(ret) - { - printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); - } - dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - - } - - ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* - (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* - (dev_drv->pixclock); // one frame time ,(pico seconds) - fps = div64_u64(1000000000000llu,ft); - screen->ft = 1000/fps ; //one frame time in ms - return fps; -} - -static int rk31_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if(order == FB_DEFAULT_ORDER) - { - order = FB0_WIN0_FB1_WIN1_FB2_WIN2; - } - dev_drv->fb2_win_id = order/100; - dev_drv->fb1_win_id = (order/10)%10; - dev_drv->fb0_win_id = order%10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, - dev_drv->fb2_win_id); - - return 0; -} - -static int rk31_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) -{ - int layer_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if(!strcmp(id,"fb0")) - { - layer_id = dev_drv->fb0_win_id; - } - else if(!strcmp(id,"fb1")) - { - layer_id = dev_drv->fb1_win_id; - } - else if(!strcmp(id,"fb2")) - { - layer_id = dev_drv->fb2_win_id; - } - else - { - printk(KERN_ERR "%s>>un supported %s\n",__func__,id); - layer_id = -1; - } - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return layer_id; -} - -int rk31_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)) - { - lcdc_dev->clk_on = 0; - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); - LCDC_REG_CFG_DONE(); - spin_unlock(&lcdc_dev->reg_lock); - } - else //clk already disabled - { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - - - mdelay(1); - clk_disable(lcdc_dev->dclk); - clk_disable(lcdc_dev->hclk); - clk_disable(lcdc_dev->aclk); - clk_disable(lcdc_dev->pd); - - return 0; -} - - -int rk31_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) -{ - struct rk31_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk31_lcdc_device,driver); - - if(!lcdc_dev->clk_on) - { - clk_enable(lcdc_dev->pd); - clk_enable(lcdc_dev->hclk); - clk_enable(lcdc_dev->dclk); - clk_enable(lcdc_dev->aclk); - } - memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->atv_layer_cnt) - { - LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); - LCDC_REG_CFG_DONE(); - } - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} -static irqreturn_t rk31_lcdc_isr(int irq, void *dev_id) -{ - struct rk31_lcdc_device *lcdc_dev = (struct rk31_lcdc_device *)dev_id; - - LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); - LCDC_REG_CFG_DONE(); - //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); - - if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync - { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - return IRQ_HANDLED; -} - -static struct layer_par lcdc_layer[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = true, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, -}; - -static struct rk_lcdc_device_driver lcdc_driver = { - .name = "lcdc", - .def_layer_par = lcdc_layer, - .num_layer = ARRAY_SIZE(lcdc_layer), - .open = rk31_lcdc_open, - .init_lcdc = init_rk31_lcdc, - .ioctl = rk31_lcdc_ioctl, - .suspend = rk31_lcdc_early_suspend, - .resume = rk31_lcdc_early_resume, - .set_par = rk31_lcdc_set_par, - .blank = rk31_lcdc_blank, - .pan_display = rk31_lcdc_pan_display, - .load_screen = rk31_load_screen, - .get_layer_state = rk31_lcdc_get_layer_state, - .ovl_mgr = rk31_lcdc_ovl_mgr, - .get_disp_info = rk31_lcdc_get_disp_info, - .fps_mgr = rk31_lcdc_fps_mgr, - .fb_get_layer = rk31_fb_get_layer, - .fb_layer_remap = rk31_fb_layer_remap, -}; -#ifdef CONFIG_PM -static int rk31_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk31_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} - -#else -#define rk31_lcdc_suspend NULL -#define rk31_lcdc_resume NULL -#endif - -static int __devinit rk31_lcdc_probe (struct platform_device *pdev) -{ - struct rk31_lcdc_device *lcdc_dev=NULL; - rk_screen *screen; - rk_screen *screen1; - struct rk29fb_info *screen_ctr_info; - struct resource *res = NULL; - struct resource *mem; - int ret = 0; - - /*************Malloc rk31lcdc_inf and set it to pdev for drvdata**********/ - lcdc_dev = kzalloc(sizeof(struct rk31_lcdc_device), GFP_KERNEL); - if(!lcdc_dev) - { - dev_err(&pdev->dev, ">>rk31 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->id = pdev->id; - screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; - screen = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen) - { - dev_err(&pdev->dev, ">>rk31 lcdc screen kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - else - { - lcdc_dev->screen = screen; - } - screen->lcdc_id = lcdc_dev->id; - screen->screen_id = 0; - -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) - screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); - if(!screen1) - { - dev_err(&pdev->dev, ">>rk31 lcdc screen1 kmalloc fail!"); - ret = -ENOMEM; - goto err0; - } - screen1->lcdc_id = 1; - screen1->screen_id = 1; - printk("use lcdc%d and rk610 implemention dual display!\n",lcdc_dev->id); - -#endif - /****************get lcdc0 reg *************************/ - res = platform_get_resource(pdev, IORESOURCE_MEM,0); - if (res == NULL) - { - dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); - if (mem == NULL) - { - dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); - ret = -ENOENT; - goto err1; - } - lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); - if (lcdc_dev->reg_vir_base == NULL) - { - dev_err(&pdev->dev, "cannot map IO\n"); - ret = -ENXIO; - goto err2; - } - - lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; - printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); - lcdc_dev->driver.dev=&pdev->dev; - lcdc_dev->driver.screen0 = screen; -#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) - lcdc_dev->driver.screen1 = screen1; -#endif - lcdc_dev->driver.cur_screen = screen; - lcdc_dev->driver.screen_ctr_info = screen_ctr_info; - spin_lock_init(&lcdc_dev->reg_lock); - lcdc_dev->irq = platform_get_irq(pdev, 0); - if(lcdc_dev->irq < 0) - { - dev_err(&pdev->dev, "cannot find IRQ\n"); - goto err3; - } - ret = request_irq(lcdc_dev->irq, rk31_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); - if (ret) - { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); - ret = -EBUSY; - goto err3; - } - ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); - if(ret < 0) - { - printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); - goto err4; - } - printk("rk31 lcdc%d probe ok!\n",lcdc_dev->id); - - return 0; - -err4: - free_irq(lcdc_dev->irq,lcdc_dev); -err3: - iounmap(lcdc_dev->reg_vir_base); -err2: - release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); -err1: - kfree(screen); -err0: - platform_set_drvdata(pdev, NULL); - kfree(lcdc_dev); - return ret; - -} -static int __devexit rk31_lcdc_remove(struct platform_device *pdev) -{ - struct rk31_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - rk_fb_unregister(&(lcdc_dev->driver)); - rk31_lcdc_deinit(lcdc_dev); - iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev); - return 0; -} - -static void rk31_lcdc_shutdown(struct platform_device *pdev) -{ - struct rk31_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary - lcdc_dev->driver.cur_screen->standby(1); - if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary - lcdc_dev->driver.screen_ctr_info->io_disable(); - if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds if necessary - lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); - rk_fb_unregister(&(lcdc_dev->driver)); - rk31_lcdc_deinit(lcdc_dev); - /*iounmap(lcdc_dev->reg_vir_base); - release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); - kfree(lcdc_dev->screen); - kfree(lcdc_dev);*/ -} - - -static struct platform_driver rk31_lcdc_driver = { - .probe = rk31_lcdc_probe, - .remove = __devexit_p(rk31_lcdc_remove), - .driver = { - .name = "rk30-lcdc", - .owner = THIS_MODULE, - }, - .suspend = rk31_lcdc_suspend, - .resume = rk31_lcdc_resume, - .shutdown = rk31_lcdc_shutdown, -}; - -static int __init rk31_lcdc_init(void) -{ - return platform_driver_register(&rk31_lcdc_driver); -} - -static void __exit rk31_lcdc_exit(void) -{ - platform_driver_unregister(&rk31_lcdc_driver); -} - - - -fs_initcall(rk31_lcdc_init); -module_exit(rk31_lcdc_exit); - - - diff --git a/drivers/video/rockchip/chips/rk31_lcdc.h b/drivers/video/rockchip/chips/rk31_lcdc.h deleted file mode 100644 index c3abd092b04b..000000000000 --- a/drivers/video/rockchip/chips/rk31_lcdc.h +++ /dev/null @@ -1,554 +0,0 @@ -/* drivers/video/rockchip/chips/rk29_fb.h - * - * Copyright (C) 2010 ROCKCHIP, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __RK31_LCDC_H -#define __RK31_LCDC_H - -#include - -#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) -#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) -#define LcdRdReg(inf, addr) (inf->preg->addr) -#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) -#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) -#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) -#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) -#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() - - -/******************************************************************** -** ºê¶¨Òå * -********************************************************************/ -/* SYS_CONFIG */ -#define m_W2_FORMAT (3<<0) -#define m_W1_FORMAT (1<<2) -#define m_W0_FORMAT (7<<3) -#define m_W0_CBR_DEFLICK_EN (1<<6) -#define m_W0_YRGB_DEFLICK_EN (1<<7) -#define m_INTERIACE_EN (1<<8) -#define m_W2_EN (1<<9) -#define m_W1_EN (1<<10) -#define m_W0_EN (1<<11) -#define m_HWC_EN (1<<12) -#define m_HWC_RELOAD_EN (1<<13) -#define m_W2_INTERLACE_READ (1<<14) -#define m_W1_INTERLACE_READ (1<<15) -#define m_W0_INTERLACE_READ (1<<16) -#define m_LCDC_STANDBY (1<<17) -#define m_HWC_BURST (3<<18) -#define m_W2_BURST (3<<20) -#define m_W1_BURST (3<<22) -#define m_W0_BURST (3<<24) -#define m_W2_LUT_CTL (1<<26) -#define m_DSIP_LUT_CTL (1<<27) -#define m_HWC_REVERSED_COLOR (1<<28) -#define m_W1_AXI_OUTSTANDING2 (1<<29) -#define m_W0_AXI_OUTSTANDING2 (1<<30) -#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) - -#define v_W2_FORMAT(x) (((x)&3)<<0) -#define v_W1_FORMAT(x) (((x)&1)<<2) -#define v_W0_FORMAT(x) (((x)&7)<<3) -#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6) -#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7) -#define v_INTERIACE_EN(x) (((x)&1)<<8) -#define v_W2_EN(x) (((x)&)1<<9) -#define v_W1_EN(x) (((x)&1)<<10) -#define v_W0_EN(x) (((x)&1)<<11) -#define v_HWC_EN(x) (((x)&1)<<12) -#define v_HWC_RELOAD_EN(x) (((x)&1)<<13) -#define v_W2_INTERLACE_READ(x) (((x)&1)<<14) -#define v_W1_INTERLACE_READ(x) (((x)&1)<<15) -#define v_W0_INTERLACE_READ(x) (((x)&1)<<16) -#define v_LCDC_STANDBY(x) (((x)&1)<<17) -#define v_HWC_BURST(x) (((x)&3)<<18) -#define v_W2_BURST(x) (((x)&3)<<20) -#define v_W1_BURST(x) (((x)&3)<<22) -#define v_W0_BURST(x) (((x)&3)<<24) -#define v_W2_LUT_CTL(x) (((x)&1)<<26) -#define v_DSIP_LUT_CTL(x) (((x)&1)<<27) -#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28) -#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29) -#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30) -#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) - -//LCDC_SWAP_CTRL -#define m_W1_565_RB_SWAP (1<<0) -#define m_W0_565_RB_SWAP (1<<1) -#define m_W0_YRGB_M8_SWAP (1<<2) -#define m_W0_YRGB_R_SHIFT_SWAP (1<<3) -#define m_W0_CBR_R_SHIFT_SWAP (1<<4) -#define m_W0_YRGB_16_SWAP (1<<5) -#define m_W0_YRGB_8_SWAP (1<<6) -#define m_W0_CBR_16_SWAP (1<<7) -#define m_W0_CBR_8_SWAP (1<<8) -#define m_W1_16_SWAP (1<<9) -#define m_W1_8_SWAP (1<<10) -#define m_W1_R_SHIFT_SWAP (1<<11) -#define m_OUTPUT_BG_SWAP (1<<12) -#define m_OUTPUT_RB_SWAP (1<<13) -#define m_OUTPUT_RG_SWAP (1<<14) -#define m_DELTA_SWAP (1<<15) -#define m_DUMMY_SWAP (1<<16) -#define m_W2_BYTE_SWAP (1<<17) -#define v_W1_565_RB_SWAP(x) (((x)&1)<<0) -#define v_W0_565_RB_SWAP(x) (((x)&1)<<1) -#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2) -#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3) -#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4) -#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5) -#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6) -#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7) -#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8) -#define v_W1_16_SWAP(x) (((x)&1)<<9) -#define v_W1_8_SWAP(x) (((x)&1)<<10) -#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11) -#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12) -#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13) -#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14) -#define v_DELTA_SWAP(x) (((x)&1)<<15) -#define v_DUMMY_SWAP(x) (((x)&1)<<16) -#define v_W2_BYTE_SWAP(x) (((x)&1)<<17) - -//LCDC_MCU_TIMING_CTRL -#define m_MCU_WRITE_PERIOD (31<<0) -#define m_MCU_CS_ST (31<<5) -#define m_MCU_CS_END (31<<10) -#define m_MCU_RW_ST (31<<15) -#define m_MCU_RW_END (31<<20) -#define m_MCU_HOLDMODE_SELECT (1<<27) -#define m_MCU_HOLDMODE_FRAME_ST (1<<28) -#define m_MCU_RS_SELECT (1<<29) -#define m_MCU_BYPASSMODE_SELECT (1<<30) -#define m_MCU_OUTPUT_SELECT (1<<31) -#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0) -#define v_MCU_CS_ST(x) (((x)&31)<<5) -#define v_MCU_CS_END(x) (((x)&31)<<10) -#define v_MCU_RW_ST(x) (((x)&31)<<15) -#define v_MCU_RW_END(x) (((x)&31)<<20) -#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26) -#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) -#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS_SELECT(x) (((x)&1)<<29) -#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) -#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) - -//LCDC_ BLEND_CTRL -#define m_HWC_BLEND_EN (1<<0) -#define m_W2_BLEND_EN (1<<1) -#define m_W1_BLEND_EN (1<<2) -#define m_W0_BLEND_EN (1<<3) -#define m_HWC_BLEND_FACTOR (15<<4) -#define m_W2_BLEND_FACTOR (0xff<<8) -#define m_W1_BLEND_FACTOR (0xff<<16) -#define m_W0_BLEND_FACTOR (0xff<<24) - -#define v_HWC_BLEND_EN(x) (((x)&1)<<0) -#define v_W2_BLEND_EN(x) (((x)&1)<<1) -#define v_W1_BLEND_EN(x) (((x)&1)<<2) -#define v_W0_BLEND_EN(x) (((x)&1)<<3) -#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) -#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) -#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) -#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) - - -//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL -#define m_KEYCOLOR (0xffffff<<0) -#define m_KEYCOLOR_B (0xff<<0) -#define m_KEYCOLOR_G (0xff<<8) -#define m_KEYCOLOR_R (0xff<<16) -#define m_COLORKEY_EN (1<<24) -#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) -#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) -#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) -#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) -#define v_COLORKEY_EN(x) (((x)&1)<<24) - -//LCDC_DEFLICKER_SCL_OFFSET -#define m_W0_YRGB_VSD_OFFSET (0xff<<0) -#define m_W0_YRGB_VSP_OFFSET (0xff<<8) -#define m_W1_VSD_OFFSET (0xff<<16) -#define m_W1_VSP_OFFSET (0xff<<24) -#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) - -//LCDC_DSP_CTRL_REG0 -#define m_DISPLAY_FORMAT (0xf<<0) -#define m_HSYNC_POLARITY (1<<4) -#define m_VSYNC_POLARITY (1<<5) -#define m_DEN_POLARITY (1<<6) -#define m_DCLK_POLARITY (1<<7) -#define m_COLOR_SPACE_CONVERSION (3<<8) -#define m_DITHER_UP_EN (1<<10) -#define m_DITHER_DOWN_MODE (1<<11) -#define m_DITHER_DOWN_EN (1<<12) -#define m_INTERLACE_FIELD_POLARITY (1<<13) -#define m_YUV_CLIP (1<<14) -#define m_W1_TRANSP_FROM (1<<15) -#define m_W0_TRANSP_FROM (1<<16) -#define m_W0W1_POSITION_SWAP (1<<17) -#define m_W1_CLIP_EN (1<<18) -#define m_W0_CLIP_EN (1<<19) -#define m_W0_YCBR_PRIORITY_MODE (1<<20) -#define m_CBR_FILTER_656 (1<<21) -#define m_W2_CHIP_EN (1<<22) - -#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) -#define v_HSYNC_POLARITY(x) (((x)&1)<<4) -#define v_VSYNC_POLARITY(x) (((x)&1)<<5) -#define v_DEN_POLARITY(x) (((x)&1)<<6) -#define v_DCLK_POLARITY(x) (((x)&1)<<7) -#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8) -#define v_DITHER_UP_EN(x) (((x)&1)<<10) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<12) -#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) -#define v_YUV_CLIP(x) (((x)&1)<<14) -#define v_W1_TRANSP_FROM(x) (((x)&1)<<15) -#define v_W0_TRANSP_FROM(x) (((x)&1)<<16) -#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<17) -#define v_W1_CLIP_EN(x) (((x)&1)<<18) -#define v_W0_CLIP_EN(x) (((x)&1)<<19) -#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20) -#define v_CBR_FILTER_656(x) (((x)&1)<<21) -#define v_W2_CHIP_EN(x) (((x)&1)<<22) - - -//LCDC_DSP_CTRL_REG1 -#define m_BG_COLOR (0xffffff<<0) -#define m_BG_B (0xff<<0) -#define m_BG_G (0xff<<8) -#define m_BG_R (0xff<<16) -#define m_BLANK_MODE (1<<24) -#define m_BLACK_MODE (1<<25) -#define m_DISP_FILTER_FACTOR (3<<26) -#define m_DISP_FILTER_MODE (1<<28) -#define m_DISP_FILTER_EN (1<<29) -#define v_BG_COLOR(x) (((x)&0xffffff)<<0) -#define v_BG_B(x) (((x)&0xff)<<0) -#define v_BG_G(x) (((x)&0xff)<<8) -#define v_BG_R(x) (((x)&0xff)<<16) -#define v_BLANK_MODE(x) (((x)&1)<<24) -#define v_BLACK_MODE(x) (((x)&1)<<25) -#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26) -#define v_DISP_FILTER_MODE(x) (((x)&1)<<28) -#define v_DISP_FILTER_EN(x) (((x)&1)<<29) - -//LCDC_INT_STATUS -#define m_HOR_START (1<<0) -#define m_FRM_START (1<<1) -#define m_SCANNING_FLAG (1<<2) -#define m_HOR_STARTMASK (1<<3) -#define m_FRM_STARTMASK (1<<4) -#define m_SCANNING_MASK (1<<5) -#define m_HOR_STARTCLEAR (1<<6) -#define m_FRM_STARTCLEAR (1<<7) -#define m_SCANNING_CLEAR (1<<8) -#define m_SCAN_LINE_NUM (0x7ff<<9) -#define v_HOR_START(x) (((x)&1)<<0) -#define v_FRM_START(x) (((x)&1)<<1) -#define v_SCANNING_FLAG(x) (((x)&1)<<2) -#define v_HOR_STARTMASK(x) (((x)&1)<<3) -#define v_FRM_STARTMASK(x) (((x)&1)<<4) -#define v_SCANNING_MASK(x) (((x)&1)<<5) -#define v_HOR_STARTCLEAR(x) (((x)&1)<<6) -#define v_FRM_STARTCLEAR(x) (((x)&1)<<7) -#define v_SCANNING_CLEAR(x) (((x)&1)<<8) -#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9) - -//AXI MS ID -#define m_W0_YRGB_CH_ID (0xF<<0) -#define m_W0_CBR_CH_ID (0xF<<4) -#define m_W1_YRGB_CH_ID (0xF<<8) -#define m_W2_CH_ID (0xF<<12) -#define m_HWC_CH_ID (0xF<<16) -#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) -#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) -#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) -#define v_W2_CH_ID(x) (((x)&0xF)<<12) -#define v_HWC_CH_ID(x) (((x)&0xF)<<16) - - -/* Low Bits Mask */ -#define m_WORDLO (0xffff<<0) -#define m_WORDHI (0xffff<<16) -#define v_WORDLO(x) (((x)&0xffff)<<0) -#define v_WORDHI(x) (((x)&0xffff)<<16) - -#define m_BIT11LO (0x7ff<<0) -#define m_BIT11HI (0x7ff<<16) -#define v_BIT11LO(x) (((x)&0x7ff)<<0) -#define v_BIT11HI(x) (((x)&0x7ff)<<16) - -#define m_BIT12LO (0xfff<<0) -#define m_BIT12HI (0xfff<<16) -#define v_BIT12LO(x) (((x)&0xfff)<<0) -#define v_BIT12HI(x) (((x)&0xfff)<<16) - - -#define m_VIRWIDTH (0xffff<<0) -#define m_VIRHEIGHT (0xffff<<16) -#define v_VIRWIDTH(x) (((x)&0xffff)<<0) -#define v_VIRHEIGHT(x) (((x)&0xffff)<<16) - -#define m_ACTWIDTH (0xffff<<0) -#define m_ACTHEIGHT (0xffff<<16) -#define v_ACTWIDTH(x) (((x)&0xffff)<<0) -#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) - -#define m_VIRST_X (0xffff<<0) -#define m_VIRST_Y (0xffff<<16) -#define v_VIRST_X(x) (((x)&0xffff)<<0) -#define v_VIRST_Y(x) (((x)&0xffff)<<16) - -#define m_PANELST_X (0x3ff<<0) -#define m_PANELST_Y (0x3ff<<16) -#define v_PANELST_X(x) (((x)&0x3ff)<<0) -#define v_PANELST_Y(x) (((x)&0x3ff)<<16) - -#define m_PANELWIDTH (0x3ff<<0) -#define m_PANELHEIGHT (0x3ff<<16) -#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) -#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) - -#define m_HWC_B (0xff<<0) -#define m_HWC_G (0xff<<8) -#define m_HWC_R (0xff<<16) -#define m_W0_YRGB_HSP_OFFSET (0xff<<24) -#define m_W0_YRGB_HSD_OFFSET (0xff<<24) -#define v_HWC_B(x) (((x)&0xff)<<0) -#define v_HWC_G(x) (((x)&0xff)<<8) -#define v_HWC_R(x) (((x)&0xff)<<16) -#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) -#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) - - -//Panel display scanning -#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) -#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) - -#define m_PANEL_END (0x3ff<<0) -#define m_PANEL_START (0x3ff<<16) -#define v_PANEL_END(x) (((x)&0x3ff)<<0) -#define v_PANEL_START(x) (((x)&0x3ff)<<16) - -#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) -#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) -#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) -#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) -//----------- - -#define m_HSCALE_FACTOR (0xffff<<0) -#define m_VSCALE_FACTOR (0xffff<<16) -#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) -#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) - -#define m_W0_CBR_HSD_OFFSET (0xff<<0) -#define m_W0_CBR_HSP_OFFSET (0xff<<8) -#define m_W0_CBR_VSD_OFFSET (0xff<<16) -#define m_W0_CBR_VSP_OFFSET (0xff<<24) -#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) -#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) -#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) -#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) - - -#define m_WIN1_FIFO_FULL_LEVEL (0x7f << 0) -#define m_WIN2_FIFO_FULL_LEVEL (0x1f << 7) -#define v_WIN1_FIFO_FULL_LEVEL(x) (((x)&0x7f) << 0) -#define v_WIN2_FIFO_FULL_LEVEL(x) (((x)&0x1f) << 7) - - -#define m_WIN0_YRGB_CHANNEL_ID ((0x0f)<<0) -#define m_WIN0_CBR_CHANNEL_ID ((0x0f)<<4) -#define m_WIN1_YRGB_CHANNEL_ID ((0x0f)<<8) -#define m_WIN2_CHANNEL_ID ((0x0f)<<12) -#define m_HWC_CHANNEL_ID ((0x0f)<<16) -#define v_WIN0_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<0) -#define v_WIN0_CBR_CHANNEL_ID(x) (((x)&0x0f)<<4) -#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<8) -#define v_WIN2_CHANNEL_ID(x) (((x)&0x0f)<<12) -#define v_HWC_CHANNEL_ID(x) (((x)&0x0f)<<16) - - -//LCDC_WINx_SCL_FACTOR_Y/CBCR -#define v_X_SCL_FACTOR(x) ((x)<<0) -#define v_Y_SCL_FACTOR(x) ((x)<<16) - -//LCDC_DSP_HTOTAL_HS_END -#define v_HSYNC(x) ((x)<<0) //hsync pulse width -#define v_HORPRD(x) ((x)<<16) //horizontal period - - -//LCDC_DSP_HACT_ST_END -#define v_HAEP(x) ((x)<<0) //horizontal active end point -#define v_HASP(x) ((x)<<16) //horizontal active start point - -//LCDC_DSP_VTOTAL_VS_END -#define v_VSYNC(x) ((x)<<0) -#define v_VERPRD(x) ((x)<<16) - -//LCDC_DSP_VACT_ST_END -#define v_VAEP(x) ((x)<<0) -#define v_VASP(x) ((x)<<16) - -//LCDC_WIN0_ACT_INFO -#define v_ACT_WIDTH(x) ((x)<<0) -#define v_ACT_HEIGHT(x) ((x)<<16) - -//LCDC_WIN0_DSP_INFO -#define v_DSP_WIDTH(x) ((x)<<0) -#define v_DSP_HEIGHT(x) ((x)<<16) - -//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning -#define v_DSP_STX(x) (x<<0) -#define v_DSP_STY(x) (x<<16) - - -/******************************************************************** -** ½á¹¹¶¨Òå * -********************************************************************/ -/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ - -typedef volatile struct tagLCDC_REG -{ - /* offset 0x00~0xc0 */ - unsigned int SYS_CFG; //0x00 SYSTEM configure register - unsigned int SWAP_CTRL; //0x04 Data SWAP control - unsigned int MCU_CTRL; //0x08 MCU TIMING control register - unsigned int BLEND_CTRL; //0x0c Blending control register - unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register - unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register - unsigned int WIN2_VIR; //0x18 WIN2 virtual display width - unsigned int DSP_CTRL0; //0x1c Display control register0 - unsigned int DSP_CTRL1; //0x20 Display control register1 - unsigned int INT_STATUS; //0x24 Interrupt status register - unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height - unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address - unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address - unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height - unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel - unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel - unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height - unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address - unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel - unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel - unsigned int WIN2_MST; //0X50 Win2 memory start address - unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel - unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel - unsigned int HWC_MST; //0x5C HWC memory start address - unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel - unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2¡¯b01 look up table 0 - unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2¡¯b10 look up table 1 - unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2¡¯b11 look up table 2 - unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point - unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point - unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point - unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point - unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode - unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode - unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting - unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting - unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset - unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark - unsigned int AXI_MS_ID; //0x98 Axi master ID - unsigned int reserved0; //0x9c - unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH - unsigned int reserved1[(0x100-0xa4)/4]; - unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port - unsigned int reserved2[(0x200-0x104)/4]; - unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port -} LCDC_REG, *pLCDC_REG; - -//roate -#define ROTATE_0 0 -#define ROTATE_90 90 -#define ROTATE_180 180 -#define ROTATE_270 270 -#define X_MIRROR (1<<10) -#define Y_MIRROR (1<<11) - - - - -#define CalScale(x, y) (((u32)x*0x1000)/y) -struct rk31_lcdc_device{ - int id; - struct rk_lcdc_device_driver driver; - rk_screen *screen; - - LCDC_REG *preg; // LCDC reg base address and backup reg - LCDC_REG regbak; - - void __iomem *reg_vir_base; // virtual basic address of lcdc register - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - struct clk *aclk_parent; //lcdc aclk divider frequency source - struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. - struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. - struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. - struct clk *pd_display; // display power domain - u32 pixclock; -}; - -struct lcdc_info{ -/*LCD CLK*/ - struct rk31_lcdc_device lcdc0; - struct rk31_lcdc_device lcdc1; - -}; - - -struct win_set { - volatile u32 y_offset; - volatile u32 c_offset; -}; - -struct win0_par { - u32 refcount; - u32 pseudo_pal[16]; - u32 y_offset; - u32 c_offset; - u32 xpos; //size in panel - u32 ypos; - u32 xsize; //start point in panel - u32 ysize; - enum data_format format; - - wait_queue_head_t wait; - struct win_set mirror; - struct win_set displ; - struct win_set done; - - u8 par_seted; - u8 addr_seted; -}; - -#endif diff --git a/drivers/video/rockchip/lcdc/rk2928_lcdc.c b/drivers/video/rockchip/lcdc/rk2928_lcdc.c new file mode 100644 index 000000000000..c991c1c62d95 --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk2928_lcdc.c @@ -0,0 +1,1123 @@ +/* + * drivers/video/rockchip/chips/rk2928_lcdc.c + * + * Copyright (C) 2012 ROCKCHIP, Inc. + *Author:yzq + * yxj + *This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk2928_lcdc.h" +#include "../lvds/rk_lvds.h" + + + + + +static int dbg_thresd = 2; +module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); +#define DBG(level,x...) do { if(unlikely(dbg_thresd > level)) printk(KERN_INFO x); } while (0) + + +static int init_rk2928_lcdc(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + if(lcdc_dev->id == 0) //lcdc0 + { + lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); + lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); + lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); + lcdc_dev->sclk = clk_get(NULL,"sclk_lcdc0"); + } + else + { + printk(KERN_ERR "invalid lcdc device!\n"); + return -EINVAL; + } + if (IS_ERR(lcdc_dev->sclk) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) + { + printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); + } + + clk_enable(lcdc_dev->pd); + clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config + clk_enable(lcdc_dev->aclk); + lcdc_dev->clk_on = 1; + LcdSetBit(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power + LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | + m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | + v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync + //LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective + return 0; +} + +static int rk2928_lcdc_deinit(struct rk2928_lcdc_device *lcdc_dev) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->clk_on = 0; + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); + LcdMskReg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN | + m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) | + v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt + LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY); + LCDC_REG_CFG_DONE(); + spin_unlock(&lcdc_dev->reg_lock); + } + else //clk already disabled + { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + mdelay(1); + + return 0; +} + +static int rk2928_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) +{ + int ret = -EINVAL; + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + rk_screen *screen = dev_drv->cur_screen; + rk_screen *screen0 = dev_drv->screen0; + u64 ft; + int fps; + u16 face; + u16 right_margin = screen->right_margin; + u16 lower_margin = screen->lower_margin; + u16 x_res = screen->x_res, y_res = screen->y_res; + DBG(1,"left_margin:%d>>hsync_len:%d>>xres:%d>>right_margin:%d>>upper_margin:%d>>vsync_len:%d>>yres:%d>>lower_margin:%d\n", + screen->left_margin,screen->hsync_len,screen->x_res,screen->right_margin,screen->upper_margin,screen->vsync_len,screen->y_res, + screen->lower_margin); + // set the rgb or mcu + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(screen->type==SCREEN_MCU) + { + printk(KERN_ERR "MCU Screen is not supported by RK2928\n"); + + } + + switch (screen->face) + { + case OUT_P565: + face = OUT_P565; + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); + break; + case OUT_P666: + face = OUT_P666; + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); + break; + case OUT_D888_P565: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); + break; + case OUT_D888_P666: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); + break; + case OUT_P888: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); + break; + default: + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); + LcdMskReg(lcdc_dev, DSP_CTRL, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); + face = screen->face; + break; + } + + //use default overlay,set vsyn hsync den dclk polarity + LcdMskReg(lcdc_dev, DSP_CTRL,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | + m_DEN_POLARITY |m_DCLK_POLARITY | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_BLACK_MODE, + v_DISPLAY_FORMAT(face) | v_HSYNC_POLARITY(screen->pin_hsync) | + v_VSYNC_POLARITY(screen->pin_vsync) | v_DEN_POLARITY(screen->pin_den) | + v_DCLK_POLARITY(screen->pin_dclk) | v_OUTPUT_RB_SWAP(screen->swap_rb) | + v_OUTPUT_RG_SWAP(screen->swap_rg) |v_BLACK_MODE(0)); + + //set background color to black,set swap according to the screen panel,disable blank mode + LcdMskReg(lcdc_dev, BG_COLOR, m_BG_COLOR ,v_BG_COLOR(0x000000)); + + + LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | + v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); + LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | + v_HASP(screen->hsync_len + screen->left_margin)); + + LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | + v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); + LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| + v_VASP(screen->vsync_len + screen->upper_margin)); + + + if(dev_drv->screen0->lcdc_id == 1) + { + //set register for scaller + LcdMskReg(lcdc_dev,SCL_REG0,m_SCL_DSP_ZERO | m_SCL_DEN_INVERT | + m_SCL_SYNC_INVERT | m_SCL_DCLK_INVERT | m_SCL_EN,v_SCL_DSP_ZERO(0) | + v_SCL_DEN_INVERT(screen0->s_den_inv) | v_SCL_SYNC_INVERT(screen0->s_hv_sync_inv) | + v_SCL_DCLK_INVERT(screen0->s_clk_inv) | v_SCL_EN(1)); + LcdWrReg(lcdc_dev,SCL_REG2,v_HASP(screen0->s_vsync_st) | v_HAEP(screen0->s_hsync_st)); + LcdWrReg(lcdc_dev,SCL_REG3,v_HASP(screen0->s_hsync_len) | + v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + + screen0->x_res + screen0->s_right_margin)); + LcdWrReg(lcdc_dev,SCL_REG4,v_HASP(screen0->s_hsync_len + screen0->s_left_margin) | + v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + screen0->x_res)); + LcdWrReg(lcdc_dev,SCL_REG5,v_VASP(screen0->s_vsync_len) | + v_VAEP(screen0->s_vsync_len + screen0->s_upper_margin + + screen0->y_res + screen0->s_lower_margin)); + LcdWrReg(lcdc_dev,SCL_REG6,v_VASP(screen0->s_vsync_len + + screen0->s_upper_margin) | v_VAEP(screen0->s_vsync_len + + screen0->s_upper_margin + screen0->y_res )); + LcdWrReg(lcdc_dev,SCL_REG8,v_VASP(screen0->s_vsync_len + screen0->s_upper_margin) | + v_VAEP(screen0->s_vsync_len + screen0->s_upper_margin + screen0->y_res)); + LcdWrReg(lcdc_dev,SCL_REG7,v_HASP(screen0->s_hsync_len + screen0->s_left_margin) | + v_HAEP(screen0->s_hsync_len + screen0->s_left_margin + screen0->x_res )); + LcdWrReg(lcdc_dev,SCL_REG1,v_SCL_V_FACTOR(0x1000)|v_SCL_H_FACTOR(0x1000)); + } + // let above to take effect + //LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + +#ifdef CONFIG_RK_LVDS + rk_lvds_register(dev_drv->screen0); +#endif + if(dev_drv->screen0->type == SCREEN_RGB) //iomux for RGB screen + { + + if(dev_drv->screen0->lcdc_id == 0) + { + rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC0_DCLK); + rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC0_HSYNC); + rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC0_VSYNC); + rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC0_DEN); + rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC0_D10); + rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC0_D11); + rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC0_D12); + rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC0_D13); + rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC0_D14); + rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC0_D15); + rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC0_D16); + rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC0_D17); + } + else if(dev_drv->screen0->lcdc_id == 1) + { + rk30_mux_api_set(GPIO2B0_LCDC0_DCLK_LCDC1_DCLK_NAME, GPIO2B_LCDC1_DCLK); + rk30_mux_api_set(GPIO2B1_LCDC0_HSYNC_LCDC1_HSYNC_NAME, GPIO2B_LCDC1_HSYNC); + rk30_mux_api_set(GPIO2B2_LCDC0_VSYNC_LCDC1_VSYNC_NAME, GPIO2B_LCDC1_VSYNC); + rk30_mux_api_set(GPIO2B3_LCDC0_DEN_LCDC1_DEN_NAME, GPIO2B_LCDC1_DEN); + rk30_mux_api_set(GPIO2B4_LCDC0_D10_LCDC1_D10_NAME, GPIO2B_LCDC1_D10); + rk30_mux_api_set(GPIO2B5_LCDC0_D11_LCDC1_D11_NAME, GPIO2B_LCDC1_D11); + rk30_mux_api_set(GPIO2B6_LCDC0_D12_LCDC1_D12_NAME, GPIO2B_LCDC1_D12); + rk30_mux_api_set(GPIO2B7_LCDC0_D13_LCDC1_D13_NAME, GPIO2B_LCDC1_D13); + rk30_mux_api_set(GPIO2C0_LCDC0_D14_LCDC1_D14_NAME, GPIO2C_LCDC1_D14); + rk30_mux_api_set(GPIO2C1_LCDC0_D15_LCDC1_D15_NAME, GPIO2C_LCDC1_D15); + rk30_mux_api_set(GPIO2C2_LCDC0_D16_LCDC1_D16_NAME, GPIO2C_LCDC1_D16); + rk30_mux_api_set(GPIO2C3_LCDC0_D17_LCDC1_D17_NAME, GPIO2C_LCDC1_D17); + } + else + { + printk(KERN_WARNING "%s>>>no such interface:%d\n",dev_drv->cur_screen->lcdc_id); + return -1; + } + + //rk30_mux_api_set(GPIO2C4_LCDC0_D18_LCDC1_D18_I2C2_SDA_NAME, GPIO2C_LCDC1_D18); + //rk30_mux_api_set(GPIO2C5_LCDC0_D19_LCDC1_D19_I2C2_SCL_NAME, GPIO2C_LCDC1_D19); + //rk30_mux_api_set(GPIO2C6_LCDC0_D20_LCDC1_D20_UART2_SIN_NAME, GPIO2C_LCDC1_D20); + //rk30_mux_api_set(GPIO2C7_LCDC0_D21_LCDC1_D21_UART2_SOUT_NAME, GPIO2C_LCDC1_D21); + //rk30_mux_api_set(GPIO2D0_LCDC0_D22_LCDC1_D22_NAME, GPIO2D_LCDC1_D22); + //rk30_mux_api_set(GPIO2D1_LCDC0_D23_LCDC1_D23_NAME, GPIO2D_LCDC1_D23); + printk("RGB screen connect to rk2928 lcdc interface%d\n",dev_drv->screen0->lcdc_id); + + } + + ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); + } + lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + clk_enable(lcdc_dev->dclk); + if(dev_drv->screen0->lcdc_id == 1) //if connect to output interface 1,need scale + { + ret = clk_set_rate(lcdc_dev->sclk, screen0->s_pixclock); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d sclk failed\n",lcdc_dev->id); + } + lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->sclk)); + //printk("%s: sclk:%lu>>need:%d",lcdc_dev->driver.name,,screen0->s_pixclock); + clk_enable(lcdc_dev->sclk); + } + + + + ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* + (dev_drv->pixclock); // one frame time ,(pico seconds) + fps = div64_u64(1000000000000llu,ft); + screen->ft = 1000/fps; + printk("%s: dclk:%lu>>sclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk), + clk_get_rate(lcdc_dev->sclk),fps); + + if(screen->init) + { + screen->init(); + } + + printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); + return 0; +} + + +//enable layer,open:1,enable;0 disable +static int win0_open(struct rk2928_lcdc_device *lcdc_dev,bool open) +{ + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(open) + { + if(!lcdc_dev->atv_layer_cnt) + { + LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); + } + lcdc_dev->atv_layer_cnt++; + } + else + { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.layer_par[0]->state = open; + + LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open)); + if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc + { + LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); + } + //LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} +static int win1_open(struct rk2928_lcdc_device *lcdc_dev,bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(open) + { + if(!lcdc_dev->atv_layer_cnt) + { + printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); + LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); + } + lcdc_dev->atv_layer_cnt++; + } + else + { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.layer_par[1]->state = open; + + LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open)); + if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc + { + printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); + LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); + } + //LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} + + +static int rk2928_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) +{ + struct rk2928_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk2928_lcdc_device ,driver); + + printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + switch(blank_mode) + { + case FB_BLANK_UNBLANK: + LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(0)); + break; + case FB_BLANK_NORMAL: + LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1)); + break; + default: + LcdMskReg(lcdc_dev,DSP_CTRL,m_BLANK_MODE ,v_BLANK_MODE(1)); + break; + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win0_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr); + LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_display(struct rk2928_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN1_RGB_MST, y_addr); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win0_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + + xact = par->xact; //active (origin) picture window width/height + yact = par->yact; + xvir = par->xvir; // virtual resolution + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor + ScaleYrgbY = CalScale(yact, par->ysize); + switch (par->format) + { + case YUV422:// yuv422 + ScaleCbrX = CalScale((xact/2), par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + case YUV420: // yuv420 + ScaleCbrX = CalScale(xact/2, par->xsize); + ScaleCbrY = CalScale(yact/2, par->ysize); + break; + case YUV444:// yuv444 + ScaleCbrX = CalScale(xact, par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + default: + break; + } + + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); + LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); + LcdMskReg(lcdc_dev, SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(par->format)); //(inf->video_mode==0) + LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); + LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); + LcdMskReg(lcdc_dev,WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, + v_COLORKEY_EN(1) | v_KEYCOLOR(0)); + switch(par->format) + { + case ARGB888: + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_ARGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB888: //rgb888 + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1)); + break; + case RGB565: //rgb565 + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB565_VIRWIDTH(xvir)); + break; + case YUV422: + case YUV420: + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_YUV_VIRWIDTH(xvir)); + break; + default: + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_WIN0_RGB888_VIRWIDTH(xvir)); + break; + } + + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_set_par(struct rk2928_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + + xact = par->xact; + yact = par->yact; + xvir = par->xvir; + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(par->format)); + LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); + // enable win1 color key and set the color to black(rgb=0) + LcdMskReg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); + + + switch(par->format) + { + case ARGB888: + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB888: //rgb888 + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir)); + // LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB565: //rgb565 + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB565_VIRWIDTH(xvir)); + break; + default: + LcdMskReg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir)); + break; + } + + + //LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + +static int rk2928_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + if(layer_id == 0) + { + win0_open(lcdc_dev,open); + } + else if(layer_id == 1) + { + win1_open(lcdc_dev,open); + } + + return 0; +} + +static int rk2928_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + struct layer_par *par = NULL; + rk_screen *screen = dev_drv->cur_screen; + rk_screen *screen0 = dev_drv->screen0; + u32 Scl_X = 0x1000; + u32 Scl_Y = 0x1000; + + if(!screen) + { + printk(KERN_ERR "screen is null!\n"); + return -ENOENT; + } + if(layer_id==0) + { + par = dev_drv->layer_par[0]; + win0_set_par(lcdc_dev,screen,par); + } + else if(layer_id==1) + { + par = dev_drv->layer_par[1]; + win1_set_par(lcdc_dev,screen,par); + } + Scl_X = CalScale(screen->x_res - 1,screen0->x_res - 1); + Scl_Y = CalScale(screen->y_res - 1 ,screen0->y_res - 1); + LcdWrReg(lcdc_dev,SCL_REG1,v_SCL_V_FACTOR(Scl_Y)|v_SCL_H_FACTOR(Scl_X)); + + return 0; +} + +int rk2928_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + struct layer_par *par = NULL; + rk_screen *screen = dev_drv->cur_screen; + unsigned long flags; + int timeout; + if(!screen) + { + printk(KERN_ERR "screen is null!\n"); + return -ENOENT; + } + if(layer_id==0) + { + par = dev_drv->layer_par[0]; + win0_display(lcdc_dev,par); + } + else if(layer_id==1) + { + par = dev_drv->layer_par[1]; + win1_display(lcdc_dev,par); + } + if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt + { + dev_drv->first_frame = 0; + LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN , + v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1)); + LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective + + } + + if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn + { + spin_lock_irqsave(&dev_drv->cpl_lock,flags); + init_completion(&dev_drv->frame_done); + spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); + timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); + if(!timeout&&(!dev_drv->frame_done.done)) + { + //printk(KERN_ERR "wait for new frame start time out!\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +int rk2928_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + u32 panel_size[2]; + void __user *argp = (void __user *)arg; + int ret = 0; + switch(cmd) + { + case FBIOGET_PANEL_SIZE: //get panel size + panel_size[0] = lcdc_dev->screen->x_res; + panel_size[1] = lcdc_dev->screen->y_res; + if(copy_to_user(argp, panel_size, 8)) + return -EFAULT; + break; + default: + break; + } + + return ret; +} +static int rk2928_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + struct layer_par *par = dev_drv->layer_par[layer_id]; + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on) + { + if(layer_id == 0) + { + par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN); + } + else if( layer_id == 1) + { + par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN); + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return par->state; + +} + +/*********************************** +overlay manager +swap:1 win0 on the top of win1 + 0 win1 on the top of win0 +set : 1 set overlay + 0 get overlay state +************************************/ +static int rk2928_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + int ovl; + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on) + { + if(set) //set overlay + { + LcdMskReg(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); + LCDC_REG_CFG_DONE(); + ovl = swap; + } + else //get overlay + { + ovl = LcdReadBit(lcdc_dev,DSP_CTRL,m_W0W1_POSITION_SWAP); + } + } + else + { + ovl = -EPERM; + } + spin_unlock(&lcdc_dev->reg_lock); + + return ovl; +} +static int rk2928_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + return 0; +} + + +/******************************************* +lcdc fps manager,set or get lcdc fps +set:0 get + 1 set +********************************************/ +static int rk2928_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + rk_screen * screen = dev_drv->cur_screen; + u64 ft = 0; + u32 dotclk; + int ret; + + if(set) + { + ft = div_u64(1000000000000llu,fps); + dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); + dotclk = div_u64(1000000000000llu,dev_drv->pixclock); + ret = clk_set_rate(lcdc_dev->dclk, dotclk); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); + } + dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + + } + + ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* + (dev_drv->pixclock); // one frame time ,(pico seconds) + fps = div64_u64(1000000000000llu,ft); + screen->ft = 1000/fps ; //one frame time in ms + return fps; +} + + +static int rk2928_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, + enum fb_win_map_order order) +{ + mutex_lock(&dev_drv->fb_win_id_mutex); + if(order == FB_DEFAULT_ORDER) + { + order = FB0_WIN0_FB1_WIN1_FB2_WIN2; + } + dev_drv->fb2_win_id = order/100; + dev_drv->fb1_win_id = (order/10)%10; + dev_drv->fb0_win_id = order%10; + mutex_unlock(&dev_drv->fb_win_id_mutex); + + printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, + dev_drv->fb2_win_id); + + return 0; +} + +static int rk2928_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) +{ + int layer_id = 0; + mutex_lock(&dev_drv->fb_win_id_mutex); + if(!strcmp(id,"fb0")) + { + layer_id = dev_drv->fb0_win_id; + } + else if(!strcmp(id,"fb1")) + { + layer_id = dev_drv->fb1_win_id; + } + else if(!strcmp(id,"fb2")) + { + layer_id = dev_drv->fb2_win_id; + } + else + { + printk(KERN_ERR "%s>>un supported %s\n",__func__,id); + layer_id = -1; + } + mutex_unlock(&dev_drv->fb_win_id_mutex); + + return layer_id; +} + +int rk2928_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + + if(dev_drv->cur_screen->sscreen_set) + dev_drv->cur_screen->sscreen_set(dev_drv->cur_screen , 0); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->clk_on = 0; + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); + LcdSetBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); + LCDC_REG_CFG_DONE(); + spin_unlock(&lcdc_dev->reg_lock); + } + else //clk already disabled + { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + + + mdelay(1); + clk_disable(lcdc_dev->dclk); + clk_disable(lcdc_dev->hclk); + clk_disable(lcdc_dev->aclk); + clk_disable(lcdc_dev->pd); + + return 0; +} + + +int rk2928_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk2928_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk2928_lcdc_device,driver); + + if(!lcdc_dev->clk_on) + { + clk_enable(lcdc_dev->pd); + clk_enable(lcdc_dev->hclk); + clk_enable(lcdc_dev->dclk); + clk_enable(lcdc_dev->aclk); + } + memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->atv_layer_cnt) + { + LcdClrBit(lcdc_dev, SYS_CFG,m_LCDC_STANDBY); + LCDC_REG_CFG_DONE(); + } + lcdc_dev->clk_on = 1; + spin_unlock(&lcdc_dev->reg_lock); + + + if(dev_drv->cur_screen->sscreen_set) + dev_drv->cur_screen->sscreen_set(dev_drv->cur_screen , 1); + + + return 0; +} +static irqreturn_t rk2928_lcdc_isr(int irq, void *dev_id) +{ + struct rk2928_lcdc_device *lcdc_dev = (struct rk2928_lcdc_device *)dev_id; + + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); + LCDC_REG_CFG_DONE(); + //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); + + if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync + { + spin_lock(&(lcdc_dev->driver.cpl_lock)); + complete(&(lcdc_dev->driver.frame_done)); + spin_unlock(&(lcdc_dev->driver.cpl_lock)); + } + return IRQ_HANDLED; +} + +static struct layer_par lcdc_layer[] = { + [0] = { + .name = "win0", + .id = 0, + .support_3d = true, + }, + [1] = { + .name = "win1", + .id = 1, + .support_3d = false, + }, +}; + +static struct rk_lcdc_device_driver lcdc_driver = { + .name = "lcdc", + .def_layer_par = lcdc_layer, + .num_layer = ARRAY_SIZE(lcdc_layer), + .open = rk2928_lcdc_open, + .init_lcdc = init_rk2928_lcdc, + .ioctl = rk2928_lcdc_ioctl, + .suspend = rk2928_lcdc_early_suspend, + .resume = rk2928_lcdc_early_resume, + .set_par = rk2928_lcdc_set_par, + .blank = rk2928_lcdc_blank, + .pan_display = rk2928_lcdc_pan_display, + .load_screen = rk2928_load_screen, + .get_layer_state = rk2928_lcdc_get_layer_state, + .ovl_mgr = rk2928_lcdc_ovl_mgr, + .get_disp_info = rk2928_lcdc_get_disp_info, + .fps_mgr = rk2928_lcdc_fps_mgr, + .fb_get_layer = rk2928_fb_get_layer, + .fb_layer_remap = rk2928_fb_layer_remap, +}; +#ifdef CONFIG_PM +static int rk2928_lcdc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int rk2928_lcdc_resume(struct platform_device *pdev) +{ + return 0; +} + +#else +#define rk2928_lcdc_suspend NULL +#define rk2928_lcdc_resume NULL +#endif + +static int __devinit rk2928_lcdc_probe (struct platform_device *pdev) +{ + struct rk2928_lcdc_device *lcdc_dev=NULL; + rk_screen *screen0; + rk_screen *screen1; + struct rk29fb_info *screen_ctr_info; + struct resource *res = NULL; + struct resource *mem; + int ret = 0; + + /*************Malloc rk2928lcdc_inf and set it to pdev for drvdata**********/ + lcdc_dev = kzalloc(sizeof(struct rk2928_lcdc_device), GFP_KERNEL); + if(!lcdc_dev) + { + dev_err(&pdev->dev, ">>rk2928 lcdc device kmalloc fail!"); + return -ENOMEM; + } + platform_set_drvdata(pdev, lcdc_dev); + lcdc_dev->id = pdev->id; + screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; + screen0 = kzalloc(sizeof(rk_screen), GFP_KERNEL); //rk2928 has one lcdc but two outputs + if(!screen0) + { + dev_err(&pdev->dev, ">>rk2928 lcdc screen1 kmalloc fail!"); + ret = -ENOMEM; + goto err0; + } + screen0->lcdc_id = 0; //this id can be changed dynamic + screen0->screen_id = 0; //this id is fixed + screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); + if(!screen1) + { + dev_err(&pdev->dev, ">>rk2928 lcdc screen1 kmalloc fail!"); + ret = -ENOMEM; + goto err0; + } + screen1->lcdc_id = 1; + screen1->screen_id = 1; + + /****************get lcdc0 reg *************************/ + res = platform_get_resource(pdev, IORESOURCE_MEM,0); + if (res == NULL) + { + dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); + ret = -ENOENT; + goto err1; + } + lcdc_dev->reg_phy_base = res->start; + lcdc_dev->len = resource_size(res); + mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); + if (mem == NULL) + { + dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); + ret = -ENOENT; + goto err1; + } + lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); + if (lcdc_dev->reg_vir_base == NULL) + { + dev_err(&pdev->dev, "cannot map IO\n"); + ret = -ENXIO; + goto err2; + } + + lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; + printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); + lcdc_dev->driver.dev=&pdev->dev; + lcdc_dev->driver.screen0 = screen0; //direct out put + lcdc_dev->driver.screen1 = screen1; //out put from scale + lcdc_dev->driver.cur_screen = screen0; + lcdc_dev->driver.screen_ctr_info = screen_ctr_info; + spin_lock_init(&lcdc_dev->reg_lock); + lcdc_dev->irq = platform_get_irq(pdev, 0); + if(lcdc_dev->irq < 0) + { + dev_err(&pdev->dev, "cannot find IRQ\n"); + goto err3; + } + ret = request_irq(lcdc_dev->irq, rk2928_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); + if (ret) + { + dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); + ret = -EBUSY; + goto err3; + } + ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); + if(ret < 0) + { + printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); + goto err4; + } + printk("rk2928 lcdc%d probe ok!\n",lcdc_dev->id); + + return 0; + +err4: + free_irq(lcdc_dev->irq,lcdc_dev); +err3: + iounmap(lcdc_dev->reg_vir_base); +err2: + release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); +err1: + kfree(screen0); +err0: + platform_set_drvdata(pdev, NULL); + kfree(lcdc_dev); + return ret; + +} +static int __devexit rk2928_lcdc_remove(struct platform_device *pdev) +{ + struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + rk_fb_unregister(&(lcdc_dev->driver)); + rk2928_lcdc_deinit(lcdc_dev); + iounmap(lcdc_dev->reg_vir_base); + release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); + kfree(lcdc_dev->screen); + kfree(lcdc_dev); + return 0; +} + +static void rk2928_lcdc_shutdown(struct platform_device *pdev) +{ + struct rk2928_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary + lcdc_dev->driver.cur_screen->standby(1); + if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary + lcdc_dev->driver.screen_ctr_info->io_disable(); + if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds + lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); + rk_fb_unregister(&(lcdc_dev->driver)); + rk2928_lcdc_deinit(lcdc_dev); + /*iounmap(lcdc_dev->reg_vir_base); + release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); + kfree(lcdc_dev->screen); + kfree(lcdc_dev);*/ +} + + +static struct platform_driver rk2928lcdc_driver = { + .probe = rk2928_lcdc_probe, + .remove = __devexit_p(rk2928_lcdc_remove), + .driver = { + .name = "rk2928-lcdc", + .owner = THIS_MODULE, + }, + .suspend = rk2928_lcdc_suspend, + .resume = rk2928_lcdc_resume, + .shutdown = rk2928_lcdc_shutdown, +}; + +static int __init rk2928_lcdc_init(void) +{ + return platform_driver_register(&rk2928lcdc_driver); +} + +static void __exit rk2928_lcdc_exit(void) +{ + platform_driver_unregister(&rk2928lcdc_driver); +} + + + +fs_initcall(rk2928_lcdc_init); +module_exit(rk2928_lcdc_exit); + + + diff --git a/drivers/video/rockchip/lcdc/rk2928_lcdc.h b/drivers/video/rockchip/lcdc/rk2928_lcdc.h new file mode 100644 index 000000000000..caa60b8d048e --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk2928_lcdc.h @@ -0,0 +1,519 @@ +#ifndef RK2928_LCDC_H_ +#define RK2928_LCDC_H_ + +#include + +#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) +#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) +#define LcdRdReg(inf, addr) (inf->preg->addr) +#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) +#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) +#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) +#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) +#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() + +/******************************************************************** +** ½á¹¹¶¨Òå * +********************************************************************/ +/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ + +typedef volatile struct tagLCDC_REG +{ + /* offset 0x00~0xc0 */ + unsigned int SYS_CFG; //0x00 system config register + unsigned int DSP_CTRL; //0x0c display control register + unsigned int BG_COLOR; //back ground color register + unsigned int ALPHA_CTRL; //alpha control register + unsigned int INT_STATUS; //0x10 Interrupt status register + unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register + unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register + unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0 + unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0 + unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height + unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height + unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel + unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel + unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting + unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting + unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset + unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address + unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel + unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel + unsigned int HWC_MST; //0x88 HWC memory start address + unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel + unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0 + unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1 + unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2 + unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point + unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point + unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point + unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point + unsigned int SCL_REG0; //scaler register + unsigned int SCL_REG1; + unsigned int SCL_REG2; + unsigned int SCL_REG3; + unsigned int SCL_REG4; + unsigned int SCL_REG5; + unsigned int SCL_REG6; + unsigned int SCL_REG7; + unsigned int SCL_REG8; + unsigned int reserve[3]; + unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH + +} LCDC_REG, *pLCDC_REG; + + +/* SYS_CONFIG */ + +#define m_W0_EN (1<<0) +#define m_W1_EN (1<<1) +#define m_HWC_EN (1<<2) +#define m_W0_FORMAT (7<<3) +#define m_W1_FORMAT (7<<6) + +#define m_W0_AXI_OUTSTANDING_DISABLE (1<<16) +#define m_W1_AXI_OUTSTANDING_DISABLE (1<<17) +#define m_DMA_BURST_LENGTH (3<<18) +#define m_LCDC_STANDBY (1<<22) + +#define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power + +#define v_W0_EN(x) (((x)&1)<<0) +#define v_W1_EN(x) (((x)&1)<<1) +#define v_HWC_EN(x) (((x)&1)<<2) +#define v_W0_FORMAT(x) (((x)&7)<<3) +#define v_W1_FORMAT(x) (((x)&7)<<6) +#define v_LCDC_STANDBY(x) (((x)&1)<<22) + +#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24) + +#define v_LCDC_DMA_STOP(x) (((x)&1)<<0) +#define v_HWC_RELOAD_EN(x) (((x)&1)<<2) +#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3) +#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4) +#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5) +#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6) +#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8) +#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11) +#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14) +#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17) +#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20) +#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23) +#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26) +#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29) + + + +//LCDC_DSP_CTRL_REG +#define m_DISPLAY_FORMAT (3<<0) +#define m_BLANK_MODE (1<<2) +#define m_BLACK_MODE (1<<3) +#define m_HSYNC_POLARITY (1<<4) +#define m_VSYNC_POLARITY (1<<5) +#define m_DEN_POLARITY (1<<6) +#define m_DCLK_POLARITY (1<<7) +#define m_W0W1_POSITION_SWAP (1<<8) +#define m_OUTPUT_BG_SWAP (1<<9) +#define m_OUTPUT_RB_SWAP (1<<10) +#define m_OUTPUT_RG_SWAP (1<<11) +#define m_DITHER_UP_EN (1<<12) +#define m_DITHER_DOWN_MODE (1<<13) +#define m_DITHER_DOWN_EN (1<<14) + + +#define m_W1_INTERLACE_READ_MODE (1<<15) +#define m_W2_INTERLACE_READ_MODE (1<<16) +#define m_W0_YRGB_DEFLICK_MODE (1<<17) +#define m_W0_CBR_DEFLICK_MODE (1<<18) +#define m_W1_YRGB_DEFLICK_MODE (1<<19) +#define m_W1_CBR_DEFLICK_MODE (1<<20) +#define m_W0_ALPHA_MODE (1<<21) +#define m_W1_ALPHA_MODE (1<<22) +#define m_W2_ALPHA_MODE (1<<23) +#define m_W0_COLOR_SPACE_CONVERSION (3<<24) +#define m_W1_COLOR_SPACE_CONVERSION (3<<26) +#define m_W2_COLOR_SPACE_CONVERSION (1<<28) +#define m_YCRCB_CLIP_EN (1<<29) +#define m_CBR_FILTER_656 (1<<30) + +#define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0) +#define v_BLANK_MODE(x) (((x)&1)<<2) +#define v_BLACK_MODE(x) (((x)&1)<<2) +#define v_HSYNC_POLARITY(x) (((x)&1)<<4) +#define v_VSYNC_POLARITY(x) (((x)&1)<<5) +#define v_DEN_POLARITY(x) (((x)&1)<<6) +#define v_DCLK_POLARITY(x) (((x)&1)<<7) +#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8) +#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9) +#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10) +#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11) +#define v_DITHER_UP_EN(x) (((x)&1)<<12) +#define v_DITHER_DOWN_MODE(x) (((x)&1)<<13) +#define v_DITHER_DOWN_EN(x) (((x)&1)<<14) + +#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) +#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) +#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14) +#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15) +#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16) +#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17) +#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18) +#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19) +#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20) +#define v_W0_ALPHA_MODE(x) (((x)&1)<<21) +#define v_W1_ALPHA_MODE(x) (((x)&1)<<22) +#define v_W2_ALPHA_MODE(x) (((x)&1)<<23) +#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24) +#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26) +#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28) +#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29) +#define v_CBR_FILTER_656(x) (((x)&1)<<30) + +//LCDC_BG_COLOR +#define m_BG_COLOR (0xffffff<<0) +#define m_BG_B (0xff<<0) +#define m_BG_G (0xff<<8) +#define m_BG_R (0xff<<16) +#define v_BG_COLOR(x) (((x)&0xffffff)<<0) +#define v_BG_B(x) (((x)&0xff)<<0) +#define v_BG_G(x) (((x)&0xff)<<8) +#define v_BG_R(x) (((x)&0xff)<<16) + + + + +//LCDC_ BLEND_CTRL +#define m_HWC_BLEND_EN (1<<0) +#define m_W2_BLEND_EN (1<<1) +#define m_W1_BLEND_EN (1<<2) +#define m_W0_BLEND_EN (1<<3) +#define m_HWC_BLEND_FACTOR (15<<4) +#define m_W2_BLEND_FACTOR (0xff<<8) +#define m_W1_BLEND_FACTOR (0xff<<16) +#define m_W0_BLEND_FACTOR (0xff<<24) + +#define v_HWC_BLEND_EN(x) (((x)&1)<<0) +#define v_W2_BLEND_EN(x) (((x)&1)<<1) +#define v_W1_BLEND_EN(x) (((x)&1)<<2) +#define v_W0_BLEND_EN(x) (((x)&1)<<3) +#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) +#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) +#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) +#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) + +//LCDC_INT_STATUS +#define v_HOR_START_INT_STA (1<<0) //status +#define v_FRM_START_INT_STA (1<<1) +#define v_LINE_FLAG_INT_STA (1<<2) +#define v_BUS_ERR_INT_STA (1<<3) +#define m_HOR_START_INT_EN (1<<4) //enable +#define m_FRM_START_INT_EN (1<<5) +#define m_LINE_FLAG_INT_EN (1<<6) +#define m_BUS_ERR_INT_EN (1<<7) +#define m_HOR_START_INT_CLEAR (1<<8) //auto clear +#define m_FRM_START_INT_CLEAR (1<<9) +#define m_LINE_FLAG_INT_CLEAR (1<<10) +#define m_BUS_ERR_INT_CLEAR (1<<11) +#define m_LINE_FLAG_NUM (0xfff<<12) +#define v_HOR_START_INT_EN(x) (((x)&1)<<4) +#define v_FRM_START_INT_EN(x) (((x)&1)<<5) +#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6) +#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) +#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8) +#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9) +#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10) +#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) +#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) + + +//LCDC_WIN_VIR +#define m_WIN0_VIR (0xfff << 0) +#define m_WIN1_VIR (0xfff << 16) +//LCDC_WINx_VIR ,x is number of words of win0 virtual width +#define v_WIN0_ARGB888_VIRWIDTH(x) (x) +#define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3)) +#define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0)) +#define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0)) + +#define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16) +#define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16) +#define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16) +#define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 ) + + +//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL +#define m_KEYCOLOR (0xffffff<<0) +#define m_KEYCOLOR_B (0xff<<0) +#define m_KEYCOLOR_G (0xff<<8) +#define m_KEYCOLOR_R (0xff<<16) +#define m_COLORKEY_EN (1<<24) +#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) +#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) +#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) +#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) +#define v_COLORKEY_EN(x) (((x)&1)<<24) + +//LCDC_DEFLICKER_SCL_OFFSET +#define m_W0_YRGB_VSD_OFFSET (0xff<<0) +#define m_W0_YRGB_VSP_OFFSET (0xff<<8) +#define m_W1_VSD_OFFSET (0xff<<16) +#define m_W1_VSP_OFFSET (0xff<<24) +#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) +#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) +#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) +#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) + + + + + +//AXI MS ID +#define m_W0_YRGB_CH_ID (0xF<<0) +#define m_W0_CBR_CH_ID (0xF<<4) +#define m_W1_YRGB_CH_ID (0xF<<8) +#define m_W2_CH_ID (0xF<<12) +#define m_HWC_CH_ID (0xF<<16) +#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) +#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) +#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) +#define v_W2_CH_ID(x) (((x)&0xF)<<12) +#define v_HWC_CH_ID(x) (((x)&0xF)<<16) + + +/* Low Bits Mask */ +#define m_WORDLO (0xffff<<0) +#define m_WORDHI (0xffff<<16) +#define v_WORDLO(x) (((x)&0xffff)<<0) +#define v_WORDHI(x) (((x)&0xffff)<<16) + + +//LCDC_WINx_SCL_FACTOR_Y/CBCR +#define v_X_SCL_FACTOR(x) ((x)<<0) +#define v_Y_SCL_FACTOR(x) ((x)<<16) + +//LCDC_DSP_HTOTAL_HS_END +#define v_HSYNC(x) ((x)<<0) //hsync pulse width +#define v_HORPRD(x) ((x)<<16) //horizontal period + + +//LCDC_DSP_HACT_ST_END +#define v_HAEP(x) ((x)<<0) //horizontal active end point +#define v_HASP(x) ((x)<<16) //horizontal active start point + +//LCDC_DSP_VTOTAL_VS_END +#define v_VSYNC(x) ((x)<<0) +#define v_VERPRD(x) ((x)<<16) + +//LCDC_DSP_VACT_ST_END +#define v_VAEP(x) ((x)<<0) +#define v_VASP(x) ((x)<<16) + + + +#define m_ACTWIDTH (0xffff<<0) +#define m_ACTHEIGHT (0xffff<<16) +#define v_ACTWIDTH(x) (((x)&0xffff)<<0) +#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) + +#define m_VIRST_X (0xffff<<0) +#define m_VIRST_Y (0xffff<<16) +#define v_VIRST_X(x) (((x)&0xffff)<<0) +#define v_VIRST_Y(x) (((x)&0xffff)<<16) + +#define m_PANELST_X (0x3ff<<0) +#define m_PANELST_Y (0x3ff<<16) +#define v_PANELST_X(x) (((x)&0x3ff)<<0) +#define v_PANELST_Y(x) (((x)&0x3ff)<<16) + +#define m_PANELWIDTH (0x3ff<<0) +#define m_PANELHEIGHT (0x3ff<<16) +#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) +#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) + +#define m_HWC_B (0xff<<0) +#define m_HWC_G (0xff<<8) +#define m_HWC_R (0xff<<16) +#define m_W0_YRGB_HSP_OFFSET (0xff<<24) +#define m_W0_YRGB_HSD_OFFSET (0xff<<24) +#define v_HWC_B(x) (((x)&0xff)<<0) +#define v_HWC_G(x) (((x)&0xff)<<8) +#define v_HWC_R(x) (((x)&0xff)<<16) +#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) +#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) + +//LCDC_WIN0_ACT_INFO +#define v_ACT_WIDTH(x) ((x-1)<<0) +#define v_ACT_HEIGHT(x) ((x-1)<<16) + +//LCDC_WIN0_DSP_INFO +#define v_DSP_WIDTH(x) ((x-1)<<0) +#define v_DSP_HEIGHT(x) ((x-1)<<16) + +//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning +#define v_DSP_STX(x) (x<<0) +#define v_DSP_STY(x) (x<<16) + +//Panel display scanning +#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) +#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) +#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) +#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) + +#define m_PANEL_END (0x3ff<<0) +#define m_PANEL_START (0x3ff<<16) +#define v_PANEL_END(x) (((x)&0x3ff)<<0) +#define v_PANEL_START(x) (((x)&0x3ff)<<16) + +#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) +#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) +#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) +#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) +//----------- + +#define m_HSCALE_FACTOR (0xffff<<0) +#define m_VSCALE_FACTOR (0xffff<<16) +#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) +#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) + +#define m_W0_CBR_HSD_OFFSET (0xff<<0) +#define m_W0_CBR_HSP_OFFSET (0xff<<8) +#define m_W0_CBR_VSD_OFFSET (0xff<<16) +#define m_W0_CBR_VSP_OFFSET (0xff<<24) +#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) +#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) +#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) +#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) + + +//LCDC_SCL_REG0 +#define m_SCL_DSP_ZERO (1<<4) +#define m_SCL_DEN_INVERT (1<<3) +#define m_SCL_SYNC_INVERT (1<<2) +#define m_SCL_DCLK_INVERT (1<<1) +#define m_SCL_EN (1<<0) +#define v_SCL_DSP_ZERO(x) (((x)&1)<<4) +#define v_SCL_DEN_INVERT(x) (((x)&1)<<3) +#define v_SCL_SYNC_INVERT(x) (((x)&1)<<2) +#define v_SCL_DCLK_INVERT(x) (((x)&1)<<1) +#define v_SCL_EN(x) (((x)&1)<<0) + +//LCDC_SCL_REG1 +#define m_SCL_V_FACTOR (0x3fff<<16) +#define m_SCL_H_FACTOR (0x3fff<<0) +#define v_SCL_V_FACTOR(x) (((x)&0x3fff)<<16) +#define v_SCL_H_FACTOR(x) (((x)&0x3fff)<<0) + + +//LCDC_SCL_REG2 +#define m_SCL_DSP_FRAME_VST (0xfff<<16) +#define m_SCL_DSP_FRAME_HST (0xfff<<0) +#define v_SCL_DSP_FRAME_VST(x) (((x)&0xfff)<<16) +#define v_SCL_DSP_FRAME_HST(x) (((x)&0xfff)<<0) + +//LCDC_SCL_REG3 +#define m_SCL_DSP_HS_END (0xff<<16) +#define m_SCL_DSP_HTOTAL (0xfff<<0) +#define v_SCL_DSP_HS_END(x) (((x)&0xff)<<16) +#define v_SCL_DSP_HTOTAL(x) (((x)&0xfff)<<0) + +//LCDC_SCL_REG4 +#define m_SCL_DSP_HACT_ST (0x3ff<<16) +#define m_SCL_DSP_HACT_END (0xfff<<0) +#define v_SCL_DSP_HACT_ST(x) (((x)&0x3ff)<<16) +#define v_SCL_DSP_HACT_END(x) (((x)&0xfff)<<0) + +//LCDC_SCL_REG5 +#define m_SCL_DSP_VS_END (0xff<<16) +#define m_SCL_DSP_VTOTAL (0xfff<<0) +#define v_SCL_DSP_VS_END(x) (((x)&0xff)<<16) +#define v_SCL_DSP_VTOTAL(x) (((x)&0xfff)<<0) + +//LCDC_SCL_REG6 +#define m_SCL_DSP_VACT_ST (0xff<<16) +#define m_SCL_DSP_VACT_END (0xfff<<0) +#define v_SCL_DSP_VACT_ST(x) (((x)&0xff)<<16) +#define v_SCL_DSP_VACT_END(x) (((x)&0xfff)<<0) + + +//LCDC_SCL_REG7 +#define m_SCL_DSP_HBOR_ST (0x3ff<<16) +#define m_SCL_DSP_HBOR_END (0xfff<<0) +#define v_SCL_DSP_HBOR_ST(x) (((x)&0x3ff)<<16) +#define v_SCL_DSP_HBOR_END(x) (((x)&0xfff)<<0) + +//LCDC_SCL_REG8 + +#define m_SCL_DSP_VBOR_ST (0xff<<16) +#define m_SCL_DSP_VBOR_END (0xfff<<0) +#define v_SCL_DSP_VBOR_ST(x) (((x)&0xff)<<16) +#define v_SCL_DSP_VBOR_END(x) (((x)&0xfff)<<0) + + + + + +#define CalScale(x, y) (((u32)(x)*0x1000)/(y)) +struct rk2928_lcdc_device{ + int id; + struct rk_lcdc_device_driver driver; + rk_screen *screen; + + LCDC_REG *preg; // LCDC reg base address and backup reg + LCDC_REG regbak; + + void __iomem *reg_vir_base; // virtual basic address of lcdc register + u32 reg_phy_base; // physical basic address of lcdc register + u32 len; // physical map length of lcdc register + spinlock_t reg_lock; //one time only one process allowed to config the register + bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed + u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc + unsigned int irq; + + struct clk *pd; //lcdc power domain + struct clk *hclk; //lcdc AHP clk + struct clk *dclk; //lcdc dclk + struct clk *aclk; //lcdc share memory frequency + struct clk *sclk; //scale clk + struct clk *aclk_parent; //lcdc aclk divider frequency source + struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. + struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. + struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. + struct clk *pd_display; // display power domain + u32 pixclock; +}; + +struct lcdc_info{ +/*LCD CLK*/ + struct rk2928_lcdc_device lcdc0; + +}; + + +struct win_set { + volatile u32 y_offset; + volatile u32 c_offset; +}; + +struct win0_par { + u32 refcount; + u32 pseudo_pal[16]; + u32 y_offset; + u32 c_offset; + u32 xpos; //size in panel + u32 ypos; + u32 xsize; //start point in panel + u32 ysize; + enum data_format format; + + wait_queue_head_t wait; + struct win_set mirror; + struct win_set displ; + struct win_set done; + + u8 par_seted; + u8 addr_seted; +}; + +#endif + + diff --git a/drivers/video/rockchip/lcdc/rk3066b_lcdc.c b/drivers/video/rockchip/lcdc/rk3066b_lcdc.c new file mode 100644 index 000000000000..2dab966b1d6f --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk3066b_lcdc.c @@ -0,0 +1,1055 @@ +/* + * drivers/video/rockchip/chips/rk3066b_lcdc.c + * + * Copyright (C) 2012 ROCKCHIP, Inc. + *Author:yzq + * yxj + *This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3066b_lcdc.h" + + + + + + +static int dbg_thresd = 0; +module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); +#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) + + +static int init_rk3066b_lcdc(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + if(lcdc_dev->id == 0) //lcdc0 + { + lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); + lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); + lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); + lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); + } + else if(lcdc_dev->id == 1) + { + lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); + lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); + lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); + lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); + } + else + { + printk(KERN_ERR "invalid lcdc device!\n"); + return -EINVAL; + } + if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) + { + printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); + } + clk_enable(lcdc_dev->pd); + clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config + clk_enable(lcdc_dev->aclk); + lcdc_dev->clk_on = 1; + + LcdMskReg(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE | m_W0_AXI_OUTSTANDING2 | + m_W1_AXI_OUTSTANDING2,v_LCDC_AXICLK_AUTO_ENABLE(1) | v_W0_AXI_OUTSTANDING2(1) | + v_W1_AXI_OUTSTANDING2(1));//eanble axi-clk auto gating for low power + LcdWrReg(lcdc_dev,AXI_MS_ID,v_HWC_CHANNEL_ID(5) | v_WIN2_CHANNEL_ID(4) | + v_WIN1_YRGB_CHANNEL_ID(3) | v_WIN0_CBR_CHANNEL_ID(2) | + v_WIN0_YRGB_CHANNEL_ID(1)); + LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | + m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | + v_SCANNING_MASK(1)); //mask all interrupt in init + LcdMskReg(lcdc_dev,FIFO_WATER_MARK,m_WIN1_FIFO_FULL_LEVEL,v_WIN1_FIFO_FULL_LEVEL(0x1e0)); + LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective + return 0; +} + +static int rk3066b_lcdc_deinit(struct rk3066b_lcdc_device *lcdc_dev) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->clk_on = 0; + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); + LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | + m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | + v_SCANNING_MASK(1)); //mask all interrupt in init + LcdSetBit(lcdc_dev,SYS_CFG,m_LCDC_STANDBY); + LCDC_REG_CFG_DONE(); + spin_unlock(&lcdc_dev->reg_lock); + } + else //clk already disabled + { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + mdelay(1); + + return 0; +} + +static int rk3066b_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) +{ + int ret = -EINVAL; + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + rk_screen *screen = dev_drv->cur_screen; + u64 ft; + int fps; + u16 face; + u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; + u16 right_margin = screen->right_margin; + u16 lower_margin = screen->lower_margin; + u16 x_res = screen->x_res, y_res = screen->y_res; + + // set the rgb or mcu + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(screen->type==SCREEN_MCU) + { + LcdMskReg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1)); + // set out format and mcu timing + mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; + if(mcu_total>31) + mcu_total = 31; + if(mcu_total<3) + mcu_total = 3; + mcu_rwstart = (mcu_total+1)/4 - 1; + mcu_rwend = ((mcu_total+1)*3)/4 - 1; + mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); + mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); + + //DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", + // mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); + + // set horizontal & vertical out timing + + right_margin = x_res/6; + screen->pixclock = 150000000; //mcu fix to 150 MHz + LcdMskReg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | + m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, + v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | + v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | + v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0)); + + } + + switch (screen->face) + { + case OUT_P565: + face = OUT_P565; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); + break; + case OUT_P666: + face = OUT_P666; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); + break; + case OUT_D888_P565: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); + break; + case OUT_D888_P666: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); + break; + case OUT_P888: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1)); + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); + break; + default: + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); + face = screen->face; + break; + } + + //use default overlay,set vsyn hsync den dclk polarity + LcdMskReg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | + m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) | + v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | + v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk)); + + //set background color to black,set swap according to the screen panel,disable blank mode + LcdMskReg(lcdc_dev, DSP_CTRL1, m_BG_COLOR | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | + m_DUMMY_SWAP | m_BLANK_MODE,v_BG_COLOR(0x000000) | v_OUTPUT_RB_SWAP(screen->swap_rb) | + v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy) | + v_BLACK_MODE(0)); + + + LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | + v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); + LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | + v_HASP(screen->hsync_len + screen->left_margin)); + + LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | + v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); + LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| + v_VASP(screen->vsync_len + screen->upper_margin)); + // let above to take effect + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); + } + lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + clk_enable(lcdc_dev->dclk); + + ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* + (dev_drv->pixclock); // one frame time ,(pico seconds) + fps = div64_u64(1000000000000llu,ft); + screen->ft = 1000/fps; + printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps); + + if(screen->init) + { + screen->init(); + } + if(screen->sscreen_set) + { + screen->sscreen_set(screen,!initscreen); + } + printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); + return 0; +} + +static int mcu_refresh(struct rk3066b_lcdc_device *lcdc_dev) +{ + + return 0; +} + + + +//enable layer,open:1,enable;0 disable +static int win0_open(struct rk3066b_lcdc_device *lcdc_dev,bool open) +{ + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(open) + { + if(!lcdc_dev->atv_layer_cnt) + { + LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); + } + lcdc_dev->atv_layer_cnt++; + } + else + { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.layer_par[0]->state = open; + + LcdMskReg(lcdc_dev, SYS_CFG, m_W0_EN, v_W0_EN(open)); + if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc + { + LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} +static int win1_open(struct rk3066b_lcdc_device *lcdc_dev,bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(open) + { + if(!lcdc_dev->atv_layer_cnt) + { + printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); + LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); + } + lcdc_dev->atv_layer_cnt++; + } + else + { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.layer_par[1]->state = open; + + LcdMskReg(lcdc_dev, SYS_CFG, m_W1_EN, v_W1_EN(open)); + if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc + { + printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); + LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} + + +static int rk3066b_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) +{ + struct rk3066b_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk3066b_lcdc_device ,driver); + + printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + switch(blank_mode) + { + case FB_BLANK_UNBLANK: + LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0)); + break; + case FB_BLANK_NORMAL: + LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); + break; + default: + LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); + break; + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win0_display(struct rk3066b_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN0_YRGB_MST,y_addr); + LcdWrReg(lcdc_dev, WIN0_CBR_MST,uv_addr); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_display(struct rk3066b_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN1_YRGB_MST, y_addr); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win0_set_par(struct rk3066b_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + u8 fmt_cfg =0 ; //data format register config value + + xact = par->xact; //active (origin) picture window width/height + yact = par->yact; + xvir = par->xvir; // virtual resolution + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + + ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor + ScaleYrgbY = CalScale(yact, par->ysize); + switch (par->format) + { + case ARGB888: + fmt_cfg = 0; + break; + case RGB565: + fmt_cfg = 1; + break; + case YUV422:// yuv422 + fmt_cfg = 2; + ScaleCbrX = CalScale((xact/2), par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + case YUV420: // yuv420 + fmt_cfg = 3; + ScaleCbrX = CalScale(xact/2, par->xsize); + ScaleCbrY = CalScale(yact/2, par->ysize); + break; + case YUV444:// yuv444 + fmt_cfg = 4; + ScaleCbrX = CalScale(xact, par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + default: + break; + } + + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); + LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); + LcdMskReg(lcdc_dev,SYS_CFG, m_W0_FORMAT, v_W0_FORMAT(fmt_cfg)); //(inf->video_mode==0) + LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); + LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); + LcdMskReg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, + v_COLORKEY_EN(0) | v_KEYCOLOR(0)); + LcdWrReg(lcdc_dev,WIN0_VIR,v_VIRWIDTH(xvir)); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_set_par(struct rk3066b_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + u8 fmt_cfg; + + xact = par->xact; + yact = par->yact; + xvir = par->xvir; + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + ScaleYrgbX = CalScale(xact, par->xsize); + ScaleYrgbY = CalScale(yact, par->ysize); + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + switch (par->format) + { + case ARGB888: + fmt_cfg = 0; + break; + case RGB565: + fmt_cfg = 1; + break; + default: + break; + } + + LcdMskReg(lcdc_dev,SYS_CFG, m_W1_FORMAT, v_W1_FORMAT(fmt_cfg)); + LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); + // enable win1 color key and set the color to black(rgb=0) + LcdMskReg(lcdc_dev,WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(0) | v_KEYCOLOR(0)); + LcdWrReg(lcdc_dev,WIN1_VIR,v_VIRWIDTH(xvir)); + + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + +static int rk3066b_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + if(layer_id == 0) + { + win0_open(lcdc_dev,open); + } + else if(layer_id == 1) + { + win1_open(lcdc_dev,open); + } + + return 0; +} + +static int rk3066b_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + struct layer_par *par = NULL; + rk_screen *screen = dev_drv->cur_screen; + if(!screen) + { + printk(KERN_ERR "screen is null!\n"); + return -ENOENT; + } + if(layer_id==0) + { + par = dev_drv->layer_par[0]; + win0_set_par(lcdc_dev,screen,par); + } + else if(layer_id==1) + { + par = dev_drv->layer_par[1]; + win1_set_par(lcdc_dev,screen,par); + } + + return 0; +} + +int rk3066b_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + struct layer_par *par = NULL; + rk_screen *screen = dev_drv->cur_screen; + unsigned long flags; + int timeout; + if(!screen) + { + printk(KERN_ERR "screen is null!\n"); + return -ENOENT; + } + if(layer_id==0) + { + par = dev_drv->layer_par[0]; + win0_display(lcdc_dev,par); + } + else if(layer_id==1) + { + par = dev_drv->layer_par[1]; + win1_display(lcdc_dev,par); + } + if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt + { + dev_drv->first_frame = 0; + LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_STARTCLEAR | m_FRM_STARTMASK , + v_FRM_STARTCLEAR(1) | v_FRM_STARTMASK(0)); + LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective + + } + + if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn + { + spin_lock_irqsave(&dev_drv->cpl_lock,flags); + init_completion(&dev_drv->frame_done); + spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); + timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); + if(!timeout&&(!dev_drv->frame_done.done)) + { + printk(KERN_ERR "wait for new frame start time out!\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +int rk3066b_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + u32 panel_size[2]; + void __user *argp = (void __user *)arg; + int ret = 0; + switch(cmd) + { + case FBIOGET_PANEL_SIZE: //get panel size + panel_size[0] = lcdc_dev->screen->x_res; + panel_size[1] = lcdc_dev->screen->y_res; + if(copy_to_user(argp, panel_size, 8)) + return -EFAULT; + break; + default: + break; + } + + return ret; +} +static int rk3066b_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + struct layer_par *par = dev_drv->layer_par[layer_id]; + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on) + { + if(layer_id == 0) + { + par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W0_EN); + } + else if( layer_id == 1) + { + par->state = LcdReadBit(lcdc_dev,SYS_CFG,m_W1_EN); + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return par->state; + +} + +/*********************************** +overlay manager +swap:1 win0 on the top of win1 + 0 win1 on the top of win0 +set : 1 set overlay + 0 get overlay state +************************************/ +static int rk3066b_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + int ovl; + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on) + { + if(set) //set overlay + { + LcdMskReg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); + LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); + LCDC_REG_CFG_DONE(); + ovl = swap; + } + else //get overlay + { + ovl = LcdReadBit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); + } + } + else + { + ovl = -EPERM; + } + spin_unlock(&lcdc_dev->reg_lock); + + return ovl; +} +static int rk3066b_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + return 0; +} + + +/******************************************* +lcdc fps manager,set or get lcdc fps +set:0 get + 1 set +********************************************/ +static int rk3066b_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + rk_screen * screen = dev_drv->cur_screen; + u64 ft = 0; + u32 dotclk; + int ret; + + if(set) + { + ft = div_u64(1000000000000llu,fps); + dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); + dotclk = div_u64(1000000000000llu,dev_drv->pixclock); + ret = clk_set_rate(lcdc_dev->dclk, dotclk); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); + } + dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + + } + + ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* + (dev_drv->pixclock); // one frame time ,(pico seconds) + fps = div64_u64(1000000000000llu,ft); + screen->ft = 1000/fps ; //one frame time in ms + return fps; +} + +static int rk3066b_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, + enum fb_win_map_order order) +{ + mutex_lock(&dev_drv->fb_win_id_mutex); + if(order == FB_DEFAULT_ORDER) + { + order = FB0_WIN0_FB1_WIN1_FB2_WIN2; + } + dev_drv->fb2_win_id = order/100; + dev_drv->fb1_win_id = (order/10)%10; + dev_drv->fb0_win_id = order%10; + mutex_unlock(&dev_drv->fb_win_id_mutex); + + printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, + dev_drv->fb2_win_id); + + return 0; +} + +static int rk3066b_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) +{ + int layer_id = 0; + mutex_lock(&dev_drv->fb_win_id_mutex); + if(!strcmp(id,"fb0")) + { + layer_id = dev_drv->fb0_win_id; + } + else if(!strcmp(id,"fb1")) + { + layer_id = dev_drv->fb1_win_id; + } + else if(!strcmp(id,"fb2")) + { + layer_id = dev_drv->fb2_win_id; + } + else + { + printk(KERN_ERR "%s>>un supported %s\n",__func__,id); + layer_id = -1; + } + mutex_unlock(&dev_drv->fb_win_id_mutex); + + return layer_id; +} + +int rk3066b_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->clk_on = 0; + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); + LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); + LCDC_REG_CFG_DONE(); + spin_unlock(&lcdc_dev->reg_lock); + } + else //clk already disabled + { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + + + mdelay(1); + clk_disable(lcdc_dev->dclk); + clk_disable(lcdc_dev->hclk); + clk_disable(lcdc_dev->aclk); + clk_disable(lcdc_dev->pd); + + return 0; +} + + +int rk3066b_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); + + if(!lcdc_dev->clk_on) + { + clk_enable(lcdc_dev->pd); + clk_enable(lcdc_dev->hclk); + clk_enable(lcdc_dev->dclk); + clk_enable(lcdc_dev->aclk); + } + memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->atv_layer_cnt) + { + LcdMskReg(lcdc_dev, SYS_CFG,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); + LCDC_REG_CFG_DONE(); + } + lcdc_dev->clk_on = 1; + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} +static irqreturn_t rk3066b_lcdc_isr(int irq, void *dev_id) +{ + struct rk3066b_lcdc_device *lcdc_dev = (struct rk3066b_lcdc_device *)dev_id; + + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_STARTCLEAR, v_FRM_STARTCLEAR(1)); + LCDC_REG_CFG_DONE(); + //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); + + if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync + { + spin_lock(&(lcdc_dev->driver.cpl_lock)); + complete(&(lcdc_dev->driver.frame_done)); + spin_unlock(&(lcdc_dev->driver.cpl_lock)); + } + return IRQ_HANDLED; +} + +static struct layer_par lcdc_layer[] = { + [0] = { + .name = "win0", + .id = 0, + .support_3d = true, + }, + [1] = { + .name = "win1", + .id = 1, + .support_3d = false, + }, +}; + +static struct rk_lcdc_device_driver lcdc_driver = { + .name = "lcdc", + .def_layer_par = lcdc_layer, + .num_layer = ARRAY_SIZE(lcdc_layer), + .open = rk3066b_lcdc_open, + .init_lcdc = init_rk3066b_lcdc, + .ioctl = rk3066b_lcdc_ioctl, + .suspend = rk3066b_lcdc_early_suspend, + .resume = rk3066b_lcdc_early_resume, + .set_par = rk3066b_lcdc_set_par, + .blank = rk3066b_lcdc_blank, + .pan_display = rk3066b_lcdc_pan_display, + .load_screen = rk3066b_load_screen, + .get_layer_state = rk3066b_lcdc_get_layer_state, + .ovl_mgr = rk3066b_lcdc_ovl_mgr, + .get_disp_info = rk3066b_lcdc_get_disp_info, + .fps_mgr = rk3066b_lcdc_fps_mgr, + .fb_get_layer = rk3066b_fb_get_layer, + .fb_layer_remap = rk3066b_fb_layer_remap, +}; +#ifdef CONFIG_PM +static int rk3066b_lcdc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int rk3066b_lcdc_resume(struct platform_device *pdev) +{ + return 0; +} + +#else +#define rk3066b_lcdc_suspend NULL +#define rk3066b_lcdc_resume NULL +#endif + +static int __devinit rk3066b_lcdc_probe (struct platform_device *pdev) +{ + struct rk3066b_lcdc_device *lcdc_dev=NULL; + rk_screen *screen; + rk_screen *screen1; + struct rk29fb_info *screen_ctr_info; + struct resource *res = NULL; + struct resource *mem; + int ret = 0; + + /*************Malloc rk3066blcdc_inf and set it to pdev for drvdata**********/ + lcdc_dev = kzalloc(sizeof(struct rk3066b_lcdc_device), GFP_KERNEL); + if(!lcdc_dev) + { + dev_err(&pdev->dev, ">>rk3066b lcdc device kmalloc fail!"); + return -ENOMEM; + } + platform_set_drvdata(pdev, lcdc_dev); + lcdc_dev->id = pdev->id; + screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; + screen = kzalloc(sizeof(rk_screen), GFP_KERNEL); + if(!screen) + { + dev_err(&pdev->dev, ">>rk3066b lcdc screen kmalloc fail!"); + ret = -ENOMEM; + goto err0; + } + else + { + lcdc_dev->screen = screen; + } + screen->lcdc_id = lcdc_dev->id; + screen->screen_id = 0; + +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + screen1 = kzalloc(sizeof(rk_screen), GFP_KERNEL); + if(!screen1) + { + dev_err(&pdev->dev, ">>rk3066b lcdc screen1 kmalloc fail!"); + ret = -ENOMEM; + goto err0; + } + screen1->lcdc_id = 1; + screen1->screen_id = 1; + printk("use lcdc%d and rk610 implemention dual display!\n",lcdc_dev->id); + +#endif + /****************get lcdc0 reg *************************/ + res = platform_get_resource(pdev, IORESOURCE_MEM,0); + if (res == NULL) + { + dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); + ret = -ENOENT; + goto err1; + } + lcdc_dev->reg_phy_base = res->start; + lcdc_dev->len = resource_size(res); + mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); + if (mem == NULL) + { + dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); + ret = -ENOENT; + goto err1; + } + lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); + if (lcdc_dev->reg_vir_base == NULL) + { + dev_err(&pdev->dev, "cannot map IO\n"); + ret = -ENXIO; + goto err2; + } + + lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; + printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); + lcdc_dev->driver.dev=&pdev->dev; + lcdc_dev->driver.screen0 = screen; +#if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& defined(CONFIG_RK610_LVDS) + lcdc_dev->driver.screen1 = screen1; +#endif + lcdc_dev->driver.cur_screen = screen; + lcdc_dev->driver.screen_ctr_info = screen_ctr_info; + spin_lock_init(&lcdc_dev->reg_lock); + lcdc_dev->irq = platform_get_irq(pdev, 0); + if(lcdc_dev->irq < 0) + { + dev_err(&pdev->dev, "cannot find IRQ\n"); + goto err3; + } + ret = request_irq(lcdc_dev->irq, rk3066b_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); + if (ret) + { + dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); + ret = -EBUSY; + goto err3; + } + ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); + if(ret < 0) + { + printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); + goto err4; + } + printk("rk3066b lcdc%d probe ok!\n",lcdc_dev->id); + + return 0; + +err4: + free_irq(lcdc_dev->irq,lcdc_dev); +err3: + iounmap(lcdc_dev->reg_vir_base); +err2: + release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); +err1: + kfree(screen); +err0: + platform_set_drvdata(pdev, NULL); + kfree(lcdc_dev); + return ret; + +} +static int __devexit rk3066b_lcdc_remove(struct platform_device *pdev) +{ + struct rk3066b_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + rk_fb_unregister(&(lcdc_dev->driver)); + rk3066b_lcdc_deinit(lcdc_dev); + iounmap(lcdc_dev->reg_vir_base); + release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); + kfree(lcdc_dev->screen); + kfree(lcdc_dev); + return 0; +} + +static void rk3066b_lcdc_shutdown(struct platform_device *pdev) +{ + struct rk3066b_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary + lcdc_dev->driver.cur_screen->standby(1); + if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary + lcdc_dev->driver.screen_ctr_info->io_disable(); + if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds if necessary + lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); + rk_fb_unregister(&(lcdc_dev->driver)); + rk3066b_lcdc_deinit(lcdc_dev); + /*iounmap(lcdc_dev->reg_vir_base); + release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); + kfree(lcdc_dev->screen); + kfree(lcdc_dev);*/ +} + + +static struct platform_driver rk3066b_lcdc_driver = { + .probe = rk3066b_lcdc_probe, + .remove = __devexit_p(rk3066b_lcdc_remove), + .driver = { + .name = "rk30-lcdc", + .owner = THIS_MODULE, + }, + .suspend = rk3066b_lcdc_suspend, + .resume = rk3066b_lcdc_resume, + .shutdown = rk3066b_lcdc_shutdown, +}; + +static int __init rk3066b_lcdc_init(void) +{ + return platform_driver_register(&rk3066b_lcdc_driver); +} + +static void __exit rk3066b_lcdc_exit(void) +{ + platform_driver_unregister(&rk3066b_lcdc_driver); +} + + + +fs_initcall(rk3066b_lcdc_init); +module_exit(rk3066b_lcdc_exit); + + + diff --git a/drivers/video/rockchip/lcdc/rk3066b_lcdc.h b/drivers/video/rockchip/lcdc/rk3066b_lcdc.h new file mode 100644 index 000000000000..d150b197fdf3 --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk3066b_lcdc.h @@ -0,0 +1,554 @@ +/* drivers/video/rockchip/chips/rk29_fb.h + * + * Copyright (C) 2010 ROCKCHIP, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __RK3066B_LCDC_H +#define __RK3066B_LCDC_H + +#include + +#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) +#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) +#define LcdRdReg(inf, addr) (inf->preg->addr) +#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) +#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) +#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) +#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) +#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() + + +/******************************************************************** +** ºê¶¨Òå * +********************************************************************/ +/* SYS_CONFIG */ +#define m_W2_FORMAT (3<<0) +#define m_W1_FORMAT (1<<2) +#define m_W0_FORMAT (7<<3) +#define m_W0_CBR_DEFLICK_EN (1<<6) +#define m_W0_YRGB_DEFLICK_EN (1<<7) +#define m_INTERIACE_EN (1<<8) +#define m_W2_EN (1<<9) +#define m_W1_EN (1<<10) +#define m_W0_EN (1<<11) +#define m_HWC_EN (1<<12) +#define m_HWC_RELOAD_EN (1<<13) +#define m_W2_INTERLACE_READ (1<<14) +#define m_W1_INTERLACE_READ (1<<15) +#define m_W0_INTERLACE_READ (1<<16) +#define m_LCDC_STANDBY (1<<17) +#define m_HWC_BURST (3<<18) +#define m_W2_BURST (3<<20) +#define m_W1_BURST (3<<22) +#define m_W0_BURST (3<<24) +#define m_W2_LUT_CTL (1<<26) +#define m_DSIP_LUT_CTL (1<<27) +#define m_HWC_REVERSED_COLOR (1<<28) +#define m_W1_AXI_OUTSTANDING2 (1<<29) +#define m_W0_AXI_OUTSTANDING2 (1<<30) +#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) + +#define v_W2_FORMAT(x) (((x)&3)<<0) +#define v_W1_FORMAT(x) (((x)&1)<<2) +#define v_W0_FORMAT(x) (((x)&7)<<3) +#define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6) +#define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7) +#define v_INTERIACE_EN(x) (((x)&1)<<8) +#define v_W2_EN(x) (((x)&)1<<9) +#define v_W1_EN(x) (((x)&1)<<10) +#define v_W0_EN(x) (((x)&1)<<11) +#define v_HWC_EN(x) (((x)&1)<<12) +#define v_HWC_RELOAD_EN(x) (((x)&1)<<13) +#define v_W2_INTERLACE_READ(x) (((x)&1)<<14) +#define v_W1_INTERLACE_READ(x) (((x)&1)<<15) +#define v_W0_INTERLACE_READ(x) (((x)&1)<<16) +#define v_LCDC_STANDBY(x) (((x)&1)<<17) +#define v_HWC_BURST(x) (((x)&3)<<18) +#define v_W2_BURST(x) (((x)&3)<<20) +#define v_W1_BURST(x) (((x)&3)<<22) +#define v_W0_BURST(x) (((x)&3)<<24) +#define v_W2_LUT_CTL(x) (((x)&1)<<26) +#define v_DSIP_LUT_CTL(x) (((x)&1)<<27) +#define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28) +#define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29) +#define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30) +#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) + +//LCDC_SWAP_CTRL +#define m_W1_565_RB_SWAP (1<<0) +#define m_W0_565_RB_SWAP (1<<1) +#define m_W0_YRGB_M8_SWAP (1<<2) +#define m_W0_YRGB_R_SHIFT_SWAP (1<<3) +#define m_W0_CBR_R_SHIFT_SWAP (1<<4) +#define m_W0_YRGB_16_SWAP (1<<5) +#define m_W0_YRGB_8_SWAP (1<<6) +#define m_W0_CBR_16_SWAP (1<<7) +#define m_W0_CBR_8_SWAP (1<<8) +#define m_W1_16_SWAP (1<<9) +#define m_W1_8_SWAP (1<<10) +#define m_W1_R_SHIFT_SWAP (1<<11) +#define m_OUTPUT_BG_SWAP (1<<12) +#define m_OUTPUT_RB_SWAP (1<<13) +#define m_OUTPUT_RG_SWAP (1<<14) +#define m_DELTA_SWAP (1<<15) +#define m_DUMMY_SWAP (1<<16) +#define m_W2_BYTE_SWAP (1<<17) +#define v_W1_565_RB_SWAP(x) (((x)&1)<<0) +#define v_W0_565_RB_SWAP(x) (((x)&1)<<1) +#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2) +#define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3) +#define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4) +#define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5) +#define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6) +#define v_W0_CBR_16_SWAP(x) (((x)&1)<<7) +#define v_W0_CBR_8_SWAP(x) (((x)&1)<<8) +#define v_W1_16_SWAP(x) (((x)&1)<<9) +#define v_W1_8_SWAP(x) (((x)&1)<<10) +#define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11) +#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12) +#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13) +#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14) +#define v_DELTA_SWAP(x) (((x)&1)<<15) +#define v_DUMMY_SWAP(x) (((x)&1)<<16) +#define v_W2_BYTE_SWAP(x) (((x)&1)<<17) + +//LCDC_MCU_TIMING_CTRL +#define m_MCU_WRITE_PERIOD (31<<0) +#define m_MCU_CS_ST (31<<5) +#define m_MCU_CS_END (31<<10) +#define m_MCU_RW_ST (31<<15) +#define m_MCU_RW_END (31<<20) +#define m_MCU_HOLDMODE_SELECT (1<<27) +#define m_MCU_HOLDMODE_FRAME_ST (1<<28) +#define m_MCU_RS_SELECT (1<<29) +#define m_MCU_BYPASSMODE_SELECT (1<<30) +#define m_MCU_OUTPUT_SELECT (1<<31) +#define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0) +#define v_MCU_CS_ST(x) (((x)&31)<<5) +#define v_MCU_CS_END(x) (((x)&31)<<10) +#define v_MCU_RW_ST(x) (((x)&31)<<15) +#define v_MCU_RW_END(x) (((x)&31)<<20) +#define v_MCU_HOLD_STATUS(x) (((x)&1)<<26) +#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) +#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) +#define v_MCU_RS_SELECT(x) (((x)&1)<<29) +#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) +#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) + +//LCDC_ BLEND_CTRL +#define m_HWC_BLEND_EN (1<<0) +#define m_W2_BLEND_EN (1<<1) +#define m_W1_BLEND_EN (1<<2) +#define m_W0_BLEND_EN (1<<3) +#define m_HWC_BLEND_FACTOR (15<<4) +#define m_W2_BLEND_FACTOR (0xff<<8) +#define m_W1_BLEND_FACTOR (0xff<<16) +#define m_W0_BLEND_FACTOR (0xff<<24) + +#define v_HWC_BLEND_EN(x) (((x)&1)<<0) +#define v_W2_BLEND_EN(x) (((x)&1)<<1) +#define v_W1_BLEND_EN(x) (((x)&1)<<2) +#define v_W0_BLEND_EN(x) (((x)&1)<<3) +#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) +#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) +#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) +#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) + + +//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL +#define m_KEYCOLOR (0xffffff<<0) +#define m_KEYCOLOR_B (0xff<<0) +#define m_KEYCOLOR_G (0xff<<8) +#define m_KEYCOLOR_R (0xff<<16) +#define m_COLORKEY_EN (1<<24) +#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) +#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) +#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) +#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) +#define v_COLORKEY_EN(x) (((x)&1)<<24) + +//LCDC_DEFLICKER_SCL_OFFSET +#define m_W0_YRGB_VSD_OFFSET (0xff<<0) +#define m_W0_YRGB_VSP_OFFSET (0xff<<8) +#define m_W1_VSD_OFFSET (0xff<<16) +#define m_W1_VSP_OFFSET (0xff<<24) +#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) +#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) +#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) +#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) + +//LCDC_DSP_CTRL_REG0 +#define m_DISPLAY_FORMAT (0xf<<0) +#define m_HSYNC_POLARITY (1<<4) +#define m_VSYNC_POLARITY (1<<5) +#define m_DEN_POLARITY (1<<6) +#define m_DCLK_POLARITY (1<<7) +#define m_COLOR_SPACE_CONVERSION (3<<8) +#define m_DITHER_UP_EN (1<<10) +#define m_DITHER_DOWN_MODE (1<<11) +#define m_DITHER_DOWN_EN (1<<12) +#define m_INTERLACE_FIELD_POLARITY (1<<13) +#define m_YUV_CLIP (1<<14) +#define m_W1_TRANSP_FROM (1<<15) +#define m_W0_TRANSP_FROM (1<<16) +#define m_W0W1_POSITION_SWAP (1<<17) +#define m_W1_CLIP_EN (1<<18) +#define m_W0_CLIP_EN (1<<19) +#define m_W0_YCBR_PRIORITY_MODE (1<<20) +#define m_CBR_FILTER_656 (1<<21) +#define m_W2_CHIP_EN (1<<22) + +#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) +#define v_HSYNC_POLARITY(x) (((x)&1)<<4) +#define v_VSYNC_POLARITY(x) (((x)&1)<<5) +#define v_DEN_POLARITY(x) (((x)&1)<<6) +#define v_DCLK_POLARITY(x) (((x)&1)<<7) +#define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8) +#define v_DITHER_UP_EN(x) (((x)&1)<<10) +#define v_DITHER_DOWN_MODE(x) (((x)&1)<<11) +#define v_DITHER_DOWN_EN(x) (((x)&1)<<12) +#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) +#define v_YUV_CLIP(x) (((x)&1)<<14) +#define v_W1_TRANSP_FROM(x) (((x)&1)<<15) +#define v_W0_TRANSP_FROM(x) (((x)&1)<<16) +#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<17) +#define v_W1_CLIP_EN(x) (((x)&1)<<18) +#define v_W0_CLIP_EN(x) (((x)&1)<<19) +#define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20) +#define v_CBR_FILTER_656(x) (((x)&1)<<21) +#define v_W2_CHIP_EN(x) (((x)&1)<<22) + + +//LCDC_DSP_CTRL_REG1 +#define m_BG_COLOR (0xffffff<<0) +#define m_BG_B (0xff<<0) +#define m_BG_G (0xff<<8) +#define m_BG_R (0xff<<16) +#define m_BLANK_MODE (1<<24) +#define m_BLACK_MODE (1<<25) +#define m_DISP_FILTER_FACTOR (3<<26) +#define m_DISP_FILTER_MODE (1<<28) +#define m_DISP_FILTER_EN (1<<29) +#define v_BG_COLOR(x) (((x)&0xffffff)<<0) +#define v_BG_B(x) (((x)&0xff)<<0) +#define v_BG_G(x) (((x)&0xff)<<8) +#define v_BG_R(x) (((x)&0xff)<<16) +#define v_BLANK_MODE(x) (((x)&1)<<24) +#define v_BLACK_MODE(x) (((x)&1)<<25) +#define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26) +#define v_DISP_FILTER_MODE(x) (((x)&1)<<28) +#define v_DISP_FILTER_EN(x) (((x)&1)<<29) + +//LCDC_INT_STATUS +#define m_HOR_START (1<<0) +#define m_FRM_START (1<<1) +#define m_SCANNING_FLAG (1<<2) +#define m_HOR_STARTMASK (1<<3) +#define m_FRM_STARTMASK (1<<4) +#define m_SCANNING_MASK (1<<5) +#define m_HOR_STARTCLEAR (1<<6) +#define m_FRM_STARTCLEAR (1<<7) +#define m_SCANNING_CLEAR (1<<8) +#define m_SCAN_LINE_NUM (0x7ff<<9) +#define v_HOR_START(x) (((x)&1)<<0) +#define v_FRM_START(x) (((x)&1)<<1) +#define v_SCANNING_FLAG(x) (((x)&1)<<2) +#define v_HOR_STARTMASK(x) (((x)&1)<<3) +#define v_FRM_STARTMASK(x) (((x)&1)<<4) +#define v_SCANNING_MASK(x) (((x)&1)<<5) +#define v_HOR_STARTCLEAR(x) (((x)&1)<<6) +#define v_FRM_STARTCLEAR(x) (((x)&1)<<7) +#define v_SCANNING_CLEAR(x) (((x)&1)<<8) +#define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9) + +//AXI MS ID +#define m_W0_YRGB_CH_ID (0xF<<0) +#define m_W0_CBR_CH_ID (0xF<<4) +#define m_W1_YRGB_CH_ID (0xF<<8) +#define m_W2_CH_ID (0xF<<12) +#define m_HWC_CH_ID (0xF<<16) +#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) +#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) +#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) +#define v_W2_CH_ID(x) (((x)&0xF)<<12) +#define v_HWC_CH_ID(x) (((x)&0xF)<<16) + + +/* Low Bits Mask */ +#define m_WORDLO (0xffff<<0) +#define m_WORDHI (0xffff<<16) +#define v_WORDLO(x) (((x)&0xffff)<<0) +#define v_WORDHI(x) (((x)&0xffff)<<16) + +#define m_BIT11LO (0x7ff<<0) +#define m_BIT11HI (0x7ff<<16) +#define v_BIT11LO(x) (((x)&0x7ff)<<0) +#define v_BIT11HI(x) (((x)&0x7ff)<<16) + +#define m_BIT12LO (0xfff<<0) +#define m_BIT12HI (0xfff<<16) +#define v_BIT12LO(x) (((x)&0xfff)<<0) +#define v_BIT12HI(x) (((x)&0xfff)<<16) + + +#define m_VIRWIDTH (0xffff<<0) +#define m_VIRHEIGHT (0xffff<<16) +#define v_VIRWIDTH(x) (((x)&0xffff)<<0) +#define v_VIRHEIGHT(x) (((x)&0xffff)<<16) + +#define m_ACTWIDTH (0xffff<<0) +#define m_ACTHEIGHT (0xffff<<16) +#define v_ACTWIDTH(x) (((x)&0xffff)<<0) +#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) + +#define m_VIRST_X (0xffff<<0) +#define m_VIRST_Y (0xffff<<16) +#define v_VIRST_X(x) (((x)&0xffff)<<0) +#define v_VIRST_Y(x) (((x)&0xffff)<<16) + +#define m_PANELST_X (0x3ff<<0) +#define m_PANELST_Y (0x3ff<<16) +#define v_PANELST_X(x) (((x)&0x3ff)<<0) +#define v_PANELST_Y(x) (((x)&0x3ff)<<16) + +#define m_PANELWIDTH (0x3ff<<0) +#define m_PANELHEIGHT (0x3ff<<16) +#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) +#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) + +#define m_HWC_B (0xff<<0) +#define m_HWC_G (0xff<<8) +#define m_HWC_R (0xff<<16) +#define m_W0_YRGB_HSP_OFFSET (0xff<<24) +#define m_W0_YRGB_HSD_OFFSET (0xff<<24) +#define v_HWC_B(x) (((x)&0xff)<<0) +#define v_HWC_G(x) (((x)&0xff)<<8) +#define v_HWC_R(x) (((x)&0xff)<<16) +#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) +#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) + + +//Panel display scanning +#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) +#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) +#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) +#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) + +#define m_PANEL_END (0x3ff<<0) +#define m_PANEL_START (0x3ff<<16) +#define v_PANEL_END(x) (((x)&0x3ff)<<0) +#define v_PANEL_START(x) (((x)&0x3ff)<<16) + +#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) +#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) +#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) +#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) +//----------- + +#define m_HSCALE_FACTOR (0xffff<<0) +#define m_VSCALE_FACTOR (0xffff<<16) +#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) +#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) + +#define m_W0_CBR_HSD_OFFSET (0xff<<0) +#define m_W0_CBR_HSP_OFFSET (0xff<<8) +#define m_W0_CBR_VSD_OFFSET (0xff<<16) +#define m_W0_CBR_VSP_OFFSET (0xff<<24) +#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) +#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) +#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) +#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) + + +#define m_WIN1_FIFO_FULL_LEVEL (0x7f << 0) +#define m_WIN2_FIFO_FULL_LEVEL (0x1f << 7) +#define v_WIN1_FIFO_FULL_LEVEL(x) (((x)&0x7f) << 0) +#define v_WIN2_FIFO_FULL_LEVEL(x) (((x)&0x1f) << 7) + + +#define m_WIN0_YRGB_CHANNEL_ID ((0x0f)<<0) +#define m_WIN0_CBR_CHANNEL_ID ((0x0f)<<4) +#define m_WIN1_YRGB_CHANNEL_ID ((0x0f)<<8) +#define m_WIN2_CHANNEL_ID ((0x0f)<<12) +#define m_HWC_CHANNEL_ID ((0x0f)<<16) +#define v_WIN0_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<0) +#define v_WIN0_CBR_CHANNEL_ID(x) (((x)&0x0f)<<4) +#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<8) +#define v_WIN2_CHANNEL_ID(x) (((x)&0x0f)<<12) +#define v_HWC_CHANNEL_ID(x) (((x)&0x0f)<<16) + + +//LCDC_WINx_SCL_FACTOR_Y/CBCR +#define v_X_SCL_FACTOR(x) ((x)<<0) +#define v_Y_SCL_FACTOR(x) ((x)<<16) + +//LCDC_DSP_HTOTAL_HS_END +#define v_HSYNC(x) ((x)<<0) //hsync pulse width +#define v_HORPRD(x) ((x)<<16) //horizontal period + + +//LCDC_DSP_HACT_ST_END +#define v_HAEP(x) ((x)<<0) //horizontal active end point +#define v_HASP(x) ((x)<<16) //horizontal active start point + +//LCDC_DSP_VTOTAL_VS_END +#define v_VSYNC(x) ((x)<<0) +#define v_VERPRD(x) ((x)<<16) + +//LCDC_DSP_VACT_ST_END +#define v_VAEP(x) ((x)<<0) +#define v_VASP(x) ((x)<<16) + +//LCDC_WIN0_ACT_INFO +#define v_ACT_WIDTH(x) ((x)<<0) +#define v_ACT_HEIGHT(x) ((x)<<16) + +//LCDC_WIN0_DSP_INFO +#define v_DSP_WIDTH(x) ((x)<<0) +#define v_DSP_HEIGHT(x) ((x)<<16) + +//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning +#define v_DSP_STX(x) (x<<0) +#define v_DSP_STY(x) (x<<16) + + +/******************************************************************** +** ½á¹¹¶¨Òå * +********************************************************************/ +/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ + +typedef volatile struct tagLCDC_REG +{ + /* offset 0x00~0xc0 */ + unsigned int SYS_CFG; //0x00 SYSTEM configure register + unsigned int SWAP_CTRL; //0x04 Data SWAP control + unsigned int MCU_CTRL; //0x08 MCU TIMING control register + unsigned int BLEND_CTRL; //0x0c Blending control register + unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register + unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register + unsigned int WIN2_VIR; //0x18 WIN2 virtual display width + unsigned int DSP_CTRL0; //0x1c Display control register0 + unsigned int DSP_CTRL1; //0x20 Display control register1 + unsigned int INT_STATUS; //0x24 Interrupt status register + unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height + unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address + unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address + unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height + unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel + unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel + unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height + unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address + unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel + unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel + unsigned int WIN2_MST; //0X50 Win2 memory start address + unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel + unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel + unsigned int HWC_MST; //0x5C HWC memory start address + unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel + unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2¡¯b01 look up table 0 + unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2¡¯b10 look up table 1 + unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2¡¯b11 look up table 2 + unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point + unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point + unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point + unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point + unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode + unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode + unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting + unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting + unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset + unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark + unsigned int AXI_MS_ID; //0x98 Axi master ID + unsigned int reserved0; //0x9c + unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH + unsigned int reserved1[(0x100-0xa4)/4]; + unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port + unsigned int reserved2[(0x200-0x104)/4]; + unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port +} LCDC_REG, *pLCDC_REG; + +//roate +#define ROTATE_0 0 +#define ROTATE_90 90 +#define ROTATE_180 180 +#define ROTATE_270 270 +#define X_MIRROR (1<<10) +#define Y_MIRROR (1<<11) + + + + +#define CalScale(x, y) (((u32)x*0x1000)/y) +struct rk3066b_lcdc_device{ + int id; + struct rk_lcdc_device_driver driver; + rk_screen *screen; + + LCDC_REG *preg; // LCDC reg base address and backup reg + LCDC_REG regbak; + + void __iomem *reg_vir_base; // virtual basic address of lcdc register + u32 reg_phy_base; // physical basic address of lcdc register + u32 len; // physical map length of lcdc register + spinlock_t reg_lock; //one time only one process allowed to config the register + bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed + u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc + + unsigned int irq; + + struct clk *pd; //lcdc power domain + struct clk *hclk; //lcdc AHP clk + struct clk *dclk; //lcdc dclk + struct clk *aclk; //lcdc share memory frequency + struct clk *aclk_parent; //lcdc aclk divider frequency source + struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. + struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. + struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. + struct clk *pd_display; // display power domain + u32 pixclock; +}; + +struct lcdc_info{ +/*LCD CLK*/ + struct rk3066b_lcdc_device lcdc0; + struct rk3066b_lcdc_device lcdc1; + +}; + + +struct win_set { + volatile u32 y_offset; + volatile u32 c_offset; +}; + +struct win0_par { + u32 refcount; + u32 pseudo_pal[16]; + u32 y_offset; + u32 c_offset; + u32 xpos; //size in panel + u32 ypos; + u32 xsize; //start point in panel + u32 ysize; + enum data_format format; + + wait_queue_head_t wait; + struct win_set mirror; + struct win_set displ; + struct win_set done; + + u8 par_seted; + u8 addr_seted; +}; + +#endif diff --git a/drivers/video/rockchip/lcdc/rk30_lcdc.c b/drivers/video/rockchip/lcdc/rk30_lcdc.c new file mode 100644 index 000000000000..3c4bfb0975f6 --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk30_lcdc.c @@ -0,0 +1,1245 @@ +/* + * drivers/video/rockchip/chips/rk30_lcdc.c + * + * Copyright (C) 2012 ROCKCHIP, Inc. + *Author:yzq + * yxj + *This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk30_lcdc.h" + + + + + + +static int dbg_thresd = 0; +module_param(dbg_thresd, int, S_IRUGO|S_IWUSR); +#define DBG(level,x...) do { if(unlikely(dbg_thresd >= level)) printk(KERN_INFO x); } while (0) + + +static int rk30_lcdc_init(struct rk_lcdc_device_driver *dev_drv) +{ + int i = 0; + int __iomem *c; + int v; + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + if(lcdc_dev->id == 0) //lcdc0 + { + lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); + lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); + lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); + lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); + } + else if(lcdc_dev->id == 1) + { + lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); + lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); + lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); + lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); + } + else + { + printk(KERN_ERR "invalid lcdc device!\n"); + return -EINVAL; + } + if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) + { + printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); + } + clk_enable(lcdc_dev->pd); + clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config + clk_enable(lcdc_dev->aclk); + lcdc_dev->clk_on = 1; + LcdMskReg(lcdc_dev,SYS_CTRL0,m_HWC_CHANNEL_ID | m_WIN2_CHANNEL_ID | m_WIN1_CBR_CHANNEL_ID | + m_WIN1_YRGB_CHANNEL_ID | m_WIN0_CBR_CHANNEL1_ID | m_WIN0_YRGB_CHANNEL1_ID | + m_WIN0_CBR_CHANNEL0_ID | m_WIN0_YRGB_CHANNEL0_ID,v_HWC_CHANNEL_ID(7) | + v_WIN2_CHANNEL_ID(6) | v_WIN1_CBR_CHANNEL_ID(5) | v_WIN1_YRGB_CHANNEL_ID(4) | + v_WIN0_CBR_CHANNEL1_ID(3) | v_WIN0_YRGB_CHANNEL1_ID(2) | v_WIN0_CBR_CHANNEL0_ID(1) | + v_WIN0_YRGB_CHANNEL0_ID(0)); //channel id ,just use default value + LcdSetBit(lcdc_dev,DSP_CTRL0, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power + LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | + m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | + v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync + if(dev_drv->cur_screen->dsp_lut) + { + LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); + LCDC_REG_CFG_DONE(); + msleep(25); + for(i=0;i<256;i++) + { + v = dev_drv->cur_screen->dsp_lut[i]; + c = lcdc_dev->dsp_lut_addr_base+i; + writel_relaxed(v,c); + + } + LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); + } + LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective + return 0; +} + +static int rk30_lcdc_deinit(struct rk30_lcdc_device *lcdc_dev) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->clk_on = 0; + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); + LcdMskReg(lcdc_dev, INT_STATUS, m_HOR_START_INT_EN | m_FRM_START_INT_EN | + m_LINE_FLAG_INT_EN | m_BUS_ERR_INT_EN,v_HOR_START_INT_EN(0) | v_FRM_START_INT_EN(0) | + v_LINE_FLAG_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt + LcdSetBit(lcdc_dev,SYS_CTRL0,m_LCDC_STANDBY); + LCDC_REG_CFG_DONE(); + spin_unlock(&lcdc_dev->reg_lock); + } + else //clk already disabled + { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + mdelay(1); + + return 0; +} + +static int rk30_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen) +{ + int ret = -EINVAL; + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + rk_screen *screen = dev_drv->cur_screen; + u64 ft; + int fps; + u16 face; + u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend; + u16 right_margin = screen->right_margin; + u16 lower_margin = screen->lower_margin; + u16 x_res = screen->x_res, y_res = screen->y_res; + + // set the rgb or mcu + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(screen->type==SCREEN_MCU) + { + LcdMskReg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1)); + // set out format and mcu timing + mcu_total = (screen->mcu_wrperiod*150*1000)/1000000; + if(mcu_total>31) + mcu_total = 31; + if(mcu_total<3) + mcu_total = 3; + mcu_rwstart = (mcu_total+1)/4 - 1; + mcu_rwend = ((mcu_total+1)*3)/4 - 1; + mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0); + mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend); + + //DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n", + // mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend); + + // set horizontal & vertical out timing + + right_margin = x_res/6; + screen->pixclock = 150000000; //mcu fix to 150 MHz + LcdMskReg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END | + m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST, + v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) | + v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) | + v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0)); + + } + + switch (screen->face) + { + case OUT_P565: + face = OUT_P565; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); + break; + case OUT_P666: + face = OUT_P666; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); + break; + case OUT_D888_P565: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0)); + break; + case OUT_D888_P666: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1)); + break; + case OUT_P888: + face = OUT_P888; + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1)); + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); + break; + default: + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0)); + LcdMskReg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0)); + face = screen->face; + break; + } + + //use default overlay,set vsyn hsync den dclk polarity + LcdMskReg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | + m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) | + v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) | + v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk)); + + //set background color to black,set swap according to the screen panel,disable blank mode + LcdMskReg(lcdc_dev, DSP_CTRL1, m_BG_COLOR | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP | + m_DUMMY_SWAP | m_BLANK_MODE,v_BG_COLOR(0x000000) | v_OUTPUT_RB_SWAP(screen->swap_rb) | + v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy) | + v_BLACK_MODE(0)); + + + LcdWrReg(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) | + v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin)); + LcdWrReg(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) | + v_HASP(screen->hsync_len + screen->left_margin)); + + LcdWrReg(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) | + v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin)); + LcdWrReg(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)| + v_VASP(screen->vsync_len + screen->upper_margin)); + // let above to take effect + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); + } + lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + clk_enable(lcdc_dev->dclk); + + ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* + (dev_drv->pixclock); // one frame time ,(pico seconds) + fps = div64_u64(1000000000000llu,ft); + screen->ft = 1000/fps; + printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps); + + if(screen->init) + { + screen->init(); + } + + printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id); + return 0; +} + +static int mcu_refresh(struct rk30_lcdc_device *lcdc_dev) +{ + + return 0; +} + + + +//enable layer,open:1,enable;0 disable +static int win0_open(struct rk30_lcdc_device *lcdc_dev,bool open) +{ + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(open) + { + if(!lcdc_dev->atv_layer_cnt) + { + LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); + } + lcdc_dev->atv_layer_cnt++; + } + else + { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.layer_par[0]->state = open; + + LcdMskReg(lcdc_dev, SYS_CTRL1, m_W0_EN, v_W0_EN(open)); + if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc + { + LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win0 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} +static int win1_open(struct rk30_lcdc_device *lcdc_dev,bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + if(open) + { + if(!lcdc_dev->atv_layer_cnt) + { + printk("lcdc%d wakeup from stanby\n",lcdc_dev->id); + LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); + } + lcdc_dev->atv_layer_cnt++; + } + else + { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.layer_par[1]->state = open; + + LcdMskReg(lcdc_dev, SYS_CTRL1, m_W1_EN, v_W1_EN(open)); + if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc + { + printk(KERN_INFO "no layer of lcdc%d is used,go to standby!",lcdc_dev->id); + LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win1 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} + +static int win2_open(struct rk30_lcdc_device *lcdc_dev,bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdMskReg(lcdc_dev, SYS_CTRL1, m_W2_EN, v_W2_EN(open)); + LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); + lcdc_dev->driver.layer_par[1]->state = open; + } + spin_unlock(&lcdc_dev->reg_lock); + printk(KERN_INFO "lcdc%d win2 %s\n",lcdc_dev->id,open?"open":"closed"); + return 0; +} + +static int rk30_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode) +{ + struct rk30_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk30_lcdc_device ,driver); + + printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + switch(blank_mode) + { + case FB_BLANK_UNBLANK: + LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0)); + break; + case FB_BLANK_NORMAL: + LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); + break; + default: + LcdMskReg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1)); + break; + } + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win0_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN0_YRGB_MST0, y_addr); + LcdWrReg(lcdc_dev, WIN0_CBR_MST0, uv_addr); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN1_YRGB_MST, y_addr); + LcdWrReg(lcdc_dev, WIN1_CBR_MST, uv_addr); + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win2_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par ) +{ + u32 y_addr; + u32 uv_addr; + y_addr = par->smem_start + par->y_offset; + uv_addr = par->cbr_start + par->c_offset; + DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN2_MST, y_addr); + LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win0_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + + xact = par->xact; //active (origin) picture window width/height + yact = par->yact; + xvir = par->xvir; // virtual resolution + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + + ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor + ScaleYrgbY = CalScale(yact, par->ysize); + switch (par->format) + { + case YUV422:// yuv422 + ScaleCbrX = CalScale((xact/2), par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + case YUV420: // yuv420 + ScaleCbrX = CalScale(xact/2, par->xsize); + ScaleCbrY = CalScale(yact/2, par->ysize); + break; + case YUV444:// yuv444 + ScaleCbrX = CalScale(xact, par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + default: + break; + } + + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); + LcdWrReg(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY)); + LcdMskReg(lcdc_dev, SYS_CTRL1, m_W0_FORMAT, v_W0_FORMAT(par->format)); //(inf->video_mode==0) + LcdWrReg(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); + LcdWrReg(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize)); + LcdMskReg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR, + v_COLORKEY_EN(1) | v_KEYCOLOR(0)); + switch(par->format) + { + case ARGB888: + LcdWrReg(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB888: //rgb888 + LcdWrReg(lcdc_dev, WIN0_VIR,v_RGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1)); + break; + case RGB565: //rgb565 + LcdWrReg(lcdc_dev, WIN0_VIR,v_RGB565_VIRWIDTH(xvir)); + break; + case YUV422: + case YUV420: + LcdWrReg(lcdc_dev, WIN0_VIR,v_YUV_VIRWIDTH(xvir)); + break; + default: + LcdWrReg(lcdc_dev, WIN0_VIR,v_RGB888_VIRWIDTH(xvir)); + break; + } + + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + + xact = par->xact; + yact = par->yact; + xvir = par->xvir; + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + ScaleYrgbX = CalScale(xact, par->xsize); + ScaleYrgbY = CalScale(yact, par->ysize); + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + switch (par->format) + { + case YUV422:// yuv422 + ScaleCbrX = CalScale((xact/2), par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + case YUV420: // yuv420 + ScaleCbrX = CalScale(xact/2, par->xsize); + ScaleCbrY = CalScale(yact/2, par->ysize); + break; + case YUV444:// yuv444 + ScaleCbrX = CalScale(xact, par->xsize); + ScaleCbrY = CalScale(yact, par->ysize); + break; + default: + break; + } + + LcdWrReg(lcdc_dev, WIN1_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY)); + LcdWrReg(lcdc_dev, WIN1_SCL_FACTOR_CBR, v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY)); + LcdMskReg(lcdc_dev,SYS_CTRL1, m_W1_FORMAT, v_W1_FORMAT(par->format)); + LcdWrReg(lcdc_dev, WIN1_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact)); + LcdWrReg(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); + // enable win1 color key and set the color to black(rgb=0) + LcdMskReg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); + switch(par->format) + { + case ARGB888: + LcdWrReg(lcdc_dev, WIN1_VIR,v_ARGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB888: //rgb888 + LcdWrReg(lcdc_dev, WIN1_VIR,v_RGB888_VIRWIDTH(xvir)); + // LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB565: //rgb565 + LcdWrReg(lcdc_dev, WIN1_VIR,v_RGB565_VIRWIDTH(xvir)); + break; + case YUV422: + case YUV420: + LcdWrReg(lcdc_dev, WIN1_VIR,v_YUV_VIRWIDTH(xvir)); + break; + default: + LcdWrReg(lcdc_dev, WIN1_VIR,v_RGB888_VIRWIDTH(xvir)); + break; + } + + LCDC_REG_CFG_DONE(); + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + +static int win2_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen, + struct layer_par *par ) +{ + u32 xact, yact, xvir, yvir, xpos, ypos; + u32 ScaleYrgbX = 0x1000; + u32 ScaleYrgbY = 0x1000; + u32 ScaleCbrX = 0x1000; + u32 ScaleCbrY = 0x1000; + + xact = par->xact; + yact = par->yact; + xvir = par->xvir; + yvir = par->yvir; + xpos = par->xpos+screen->left_margin + screen->hsync_len; + ypos = par->ypos+screen->upper_margin + screen->vsync_len; + + ScaleYrgbX = CalScale(xact, par->xsize); + ScaleYrgbY = CalScale(yact, par->ysize); + DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", + __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos); + + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + + LcdMskReg(lcdc_dev,SYS_CTRL1, m_W2_FORMAT, v_W2_FORMAT(par->format)); + LcdWrReg(lcdc_dev, WIN2_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos)); + LcdWrReg(lcdc_dev, WIN2_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize)); + // enable win1 color key and set the color to black(rgb=0) + LcdMskReg(lcdc_dev, WIN2_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0)); + switch(par->format) + { + case ARGB888: + LcdWrReg(lcdc_dev, WIN2_VIR,v_ARGB888_VIRWIDTH(xvir)); + //LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB888: //rgb888 + LcdWrReg(lcdc_dev, WIN2_VIR,v_RGB888_VIRWIDTH(xvir)); + // LcdMskReg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1)); + break; + case RGB565: //rgb565 + LcdWrReg(lcdc_dev, WIN2_VIR,v_RGB565_VIRWIDTH(xvir)); + break; + case YUV422: + case YUV420: + LcdWrReg(lcdc_dev, WIN2_VIR,v_YUV_VIRWIDTH(xvir)); + break; + default: + LcdWrReg(lcdc_dev, WIN2_VIR,v_RGB888_VIRWIDTH(xvir)); + break; + } + + LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + +static int rk30_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + if(layer_id == 0) + { + win0_open(lcdc_dev,open); + } + else if(layer_id == 1) + { + win1_open(lcdc_dev,open); + } + else if(layer_id == 2) + { + win2_open(lcdc_dev,open); + } + + return 0; +} + +static int rk30_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + struct layer_par *par = NULL; + rk_screen *screen = dev_drv->cur_screen; + if(!screen) + { + printk(KERN_ERR "screen is null!\n"); + return -ENOENT; + } + if(layer_id==0) + { + par = dev_drv->layer_par[0]; + win0_set_par(lcdc_dev,screen,par); + } + else if(layer_id==1) + { + par = dev_drv->layer_par[1]; + win1_set_par(lcdc_dev,screen,par); + } + else if(layer_id == 2) + { + par = dev_drv->layer_par[2]; + win2_set_par(lcdc_dev,screen,par); + } + + return 0; +} + +int rk30_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + struct layer_par *par = NULL; + rk_screen *screen = dev_drv->cur_screen; + unsigned long flags; + int timeout; + if(!screen) + { + printk(KERN_ERR "screen is null!\n"); + return -ENOENT; + } + if(layer_id==0) + { + par = dev_drv->layer_par[0]; + win0_display(lcdc_dev,par); + } + else if(layer_id==1) + { + par = dev_drv->layer_par[1]; + win1_display(lcdc_dev,par); + } + else if(layer_id == 2) + { + par = dev_drv->layer_par[2]; + win2_display(lcdc_dev,par); + } + if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt + { + dev_drv->first_frame = 0; + LcdMskReg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN , + v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1)); + LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective + + } + + if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn + { + spin_lock_irqsave(&dev_drv->cpl_lock,flags); + init_completion(&dev_drv->frame_done); + spin_unlock_irqrestore(&dev_drv->cpl_lock,flags); + timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5)); + if(!timeout&&(!dev_drv->frame_done.done)) + { + printk(KERN_ERR "wait for new frame start time out!\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +int rk30_lcdc_ioctl(struct rk_lcdc_device_driver * dev_drv,unsigned int cmd, unsigned long arg,int layer_id) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + u32 panel_size[2]; + void __user *argp = (void __user *)arg; + int ret = 0; + switch(cmd) + { + case FBIOGET_PANEL_SIZE: //get panel size + panel_size[0] = dev_drv->screen0->x_res; + panel_size[1] = dev_drv->screen0->y_res; + if(copy_to_user(argp, panel_size, 8)) + return -EFAULT; + break; + default: + break; + } + + return ret; +} +static int rk30_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + struct layer_par *par = dev_drv->layer_par[layer_id]; + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on) + { + if(layer_id == 0) + { + par->state = LcdReadBit(lcdc_dev,SYS_CTRL1,m_W0_EN); + } + else if( layer_id == 1) + { + par->state = LcdReadBit(lcdc_dev,SYS_CTRL1,m_W1_EN); + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return par->state; + +} + +/*********************************** +overlay manager +swap:1 win0 on the top of win1 + 0 win1 on the top of win0 +set : 1 set overlay + 0 get overlay state +************************************/ +static int rk30_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + int ovl; + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on) + { + if(set) //set overlay + { + LcdMskReg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap)); + LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); + LCDC_REG_CFG_DONE(); + ovl = swap; + } + else //get overlay + { + ovl = LcdReadBit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP); + } + } + else + { + ovl = -EPERM; + } + spin_unlock(&lcdc_dev->reg_lock); + + return ovl; +} +static int rk30_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,int layer_id) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + return 0; +} + + +/******************************************* +lcdc fps manager,set or get lcdc fps +set:0 get + 1 set +********************************************/ +static int rk30_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + rk_screen * screen = dev_drv->cur_screen; + u64 ft = 0; + u32 dotclk; + int ret; + + if(set) + { + ft = div_u64(1000000000000llu,fps); + dev_drv->pixclock = div_u64(ft,(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)); + dotclk = div_u64(1000000000000llu,dev_drv->pixclock); + ret = clk_set_rate(lcdc_dev->dclk, dotclk); + if(ret) + { + printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id); + } + dev_drv->pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + + } + + ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)* + (screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)* + (dev_drv->pixclock); // one frame time ,(pico seconds) + fps = div64_u64(1000000000000llu,ft); + screen->ft = 1000/fps ; //one frame time in ms + return fps; +} + +static int rk30_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv, + enum fb_win_map_order order) +{ + mutex_lock(&dev_drv->fb_win_id_mutex); + if(order == FB_DEFAULT_ORDER ) + { + order = FB0_WIN1_FB1_WIN0_FB2_WIN2; + } + dev_drv->fb2_win_id = order/100; + dev_drv->fb1_win_id = (order/10)%10; + dev_drv->fb0_win_id = order%10; + mutex_unlock(&dev_drv->fb_win_id_mutex); + + printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id, + dev_drv->fb2_win_id); + + return 0; +} + +static int rk30_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id) +{ + int layer_id = 0; + mutex_lock(&dev_drv->fb_win_id_mutex); + if(!strcmp(id,"fb0")||!strcmp(id,"fb3")) + { + layer_id = dev_drv->fb0_win_id; + } + else if(!strcmp(id,"fb1")||!strcmp(id,"fb4")) + { + layer_id = dev_drv->fb1_win_id; + } + else if(!strcmp(id,"fb2")||!strcmp(id,"fb5")) + { + layer_id = dev_drv->fb2_win_id; + } + mutex_unlock(&dev_drv->fb_win_id_mutex); + + return layer_id; +} + +static int rk30_read_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) +{ + + return 0; +} + +static int rk30_set_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut) +{ + int i=0; + int __iomem *c; + int v; + int ret = 0; + + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); + LCDC_REG_CFG_DONE(); + msleep(25); + if(dev_drv->cur_screen->dsp_lut) + { + for(i=0;i<256;i++) + { + v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; + c = lcdc_dev->dsp_lut_addr_base+i; + writel_relaxed(v,c); + + } + } + else + { + printk(KERN_WARNING "no buffer to backup lut data!\n"); + ret = -1; + } + LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); + LCDC_REG_CFG_DONE(); + + return ret; +} +int rk30_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->clk_on = 0; + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); + LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1)); + LCDC_REG_CFG_DONE(); + spin_unlock(&lcdc_dev->reg_lock); + } + else //clk already disabled + { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + + + mdelay(1); + clk_disable(lcdc_dev->dclk); + clk_disable(lcdc_dev->hclk); + clk_disable(lcdc_dev->aclk); + clk_disable(lcdc_dev->pd); + + return 0; +} + + +int rk30_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv) +{ + struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); + int i=0; + int __iomem *c; + int v; + if(!lcdc_dev->clk_on) + { + clk_enable(lcdc_dev->pd); + clk_enable(lcdc_dev->hclk); + clk_enable(lcdc_dev->dclk); + clk_enable(lcdc_dev->aclk); + } + memcpy((u8*)lcdc_dev->preg, (u8*)&lcdc_dev->regbak, 0xc4); //resume reg + + spin_lock(&lcdc_dev->reg_lock); + if(dev_drv->cur_screen->dsp_lut) //resume dsp lut + { + LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); + LCDC_REG_CFG_DONE(); + mdelay(25); + for(i=0;i<256;i++) + { + v = dev_drv->cur_screen->dsp_lut[i]; + c = lcdc_dev->dsp_lut_addr_base+i; + writel_relaxed(v,c); + + } + LcdMskReg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); + } + if(lcdc_dev->atv_layer_cnt) + { + LcdMskReg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0)); + LCDC_REG_CFG_DONE(); + } + lcdc_dev->clk_on = 1; + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} +static irqreturn_t rk30_lcdc_isr(int irq, void *dev_id) +{ + struct rk30_lcdc_device *lcdc_dev = (struct rk30_lcdc_device *)dev_id; + + LcdMskReg(lcdc_dev, INT_STATUS, m_FRM_START_INT_CLEAR, v_FRM_START_INT_CLEAR(1)); + LCDC_REG_CFG_DONE(); + //LcdMskReg(lcdc_dev, INT_STATUS, m_LINE_FLAG_INT_CLEAR, v_LINE_FLAG_INT_CLEAR(1)); + + if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync + { + spin_lock(&(lcdc_dev->driver.cpl_lock)); + complete(&(lcdc_dev->driver.frame_done)); + spin_unlock(&(lcdc_dev->driver.cpl_lock)); + } + return IRQ_HANDLED; +} + +static struct layer_par lcdc_layer[] = { + [0] = { + .name = "win0", + .id = 0, + .support_3d = true, + }, + [1] = { + .name = "win1", + .id = 1, + .support_3d = false, + }, + [2] = { + .name = "win2", + .id = 2, + .support_3d = false, + }, +}; + +static struct rk_lcdc_device_driver lcdc_driver = { + .name = "lcdc", + .def_layer_par = lcdc_layer, + .num_layer = ARRAY_SIZE(lcdc_layer), + .open = rk30_lcdc_open, + .init_lcdc = rk30_lcdc_init, + .ioctl = rk30_lcdc_ioctl, + .suspend = rk30_lcdc_early_suspend, + .resume = rk30_lcdc_early_resume, + .set_par = rk30_lcdc_set_par, + .blank = rk30_lcdc_blank, + .pan_display = rk30_lcdc_pan_display, + .load_screen = rk30_load_screen, + .get_layer_state = rk30_lcdc_get_layer_state, + .ovl_mgr = rk30_lcdc_ovl_mgr, + .get_disp_info = rk30_lcdc_get_disp_info, + .fps_mgr = rk30_lcdc_fps_mgr, + .fb_get_layer = rk30_fb_get_layer, + .fb_layer_remap = rk30_fb_layer_remap, + .set_dsp_lut = rk30_set_dsp_lut, + .read_dsp_lut = rk30_read_dsp_lut, +}; +#ifdef CONFIG_PM +static int rk30_lcdc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int rk30_lcdc_resume(struct platform_device *pdev) +{ + return 0; +} + +#else +#define rk30_lcdc_suspend NULL +#define rk30_lcdc_resume NULL +#endif + +static int __devinit rk30_lcdc_probe (struct platform_device *pdev) +{ + struct rk30_lcdc_device *lcdc_dev=NULL; + rk_screen *screen; + struct rk29fb_info *screen_ctr_info; + struct resource *res = NULL; + struct resource *mem; + int ret = 0; + + /*************Malloc rk30lcdc_inf and set it to pdev for drvdata**********/ + lcdc_dev = kzalloc(sizeof(struct rk30_lcdc_device), GFP_KERNEL); + if(!lcdc_dev) + { + dev_err(&pdev->dev, ">>rk30 lcdc device kmalloc fail!"); + return -ENOMEM; + } + platform_set_drvdata(pdev, lcdc_dev); + lcdc_dev->id = pdev->id; + screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data; + screen = kzalloc(sizeof(rk_screen), GFP_KERNEL); + if(!screen) + { + dev_err(&pdev->dev, ">>rk30 lcdc screen kmalloc fail!"); + ret = -ENOMEM; + goto err0; + } + /****************get lcdc0 reg *************************/ + res = platform_get_resource(pdev, IORESOURCE_MEM,0); + if (res == NULL) + { + dev_err(&pdev->dev, "failed to get io resource for lcdc%d \n",lcdc_dev->id); + ret = -ENOENT; + goto err1; + } + lcdc_dev->reg_phy_base = res->start; + lcdc_dev->len = resource_size(res); + mem = request_mem_region(lcdc_dev->reg_phy_base, resource_size(res), pdev->name); + if (mem == NULL) + { + dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id); + ret = -ENOENT; + goto err1; + } + lcdc_dev->reg_vir_base = ioremap(lcdc_dev->reg_phy_base, resource_size(res)); + if (lcdc_dev->reg_vir_base == NULL) + { + dev_err(&pdev->dev, "cannot map IO\n"); + ret = -ENXIO; + goto err2; + } + + lcdc_dev->preg = (LCDC_REG*)lcdc_dev->reg_vir_base; + lcdc_dev->dsp_lut_addr_base = &lcdc_dev->preg->DSP_LUT_ADDR; + printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->preg); + lcdc_dev->driver.dev=&pdev->dev; + lcdc_dev->driver.screen0 = screen; + lcdc_dev->driver.cur_screen = screen; + lcdc_dev->driver.screen_ctr_info = screen_ctr_info; + spin_lock_init(&lcdc_dev->reg_lock); + lcdc_dev->irq = platform_get_irq(pdev, 0); + if(lcdc_dev->irq < 0) + { + dev_err(&pdev->dev, "cannot find IRQ\n"); + goto err3; + } + ret = request_irq(lcdc_dev->irq, rk30_lcdc_isr, IRQF_DISABLED,dev_name(&pdev->dev),lcdc_dev); + if (ret) + { + dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret); + ret = -EBUSY; + goto err3; + } + ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id); + if(ret < 0) + { + printk(KERN_ERR "register fb for lcdc%d failed!\n",lcdc_dev->id); + goto err4; + } + printk("rk30 lcdc%d probe ok!\n",lcdc_dev->id); + + return 0; + +err4: + free_irq(lcdc_dev->irq,lcdc_dev); +err3: + iounmap(lcdc_dev->reg_vir_base); +err2: + release_mem_region(lcdc_dev->reg_phy_base,resource_size(res)); +err1: + kfree(screen); +err0: + platform_set_drvdata(pdev, NULL); + kfree(lcdc_dev); + return ret; + +} +static int __devexit rk30_lcdc_remove(struct platform_device *pdev) +{ + struct rk30_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + rk_fb_unregister(&(lcdc_dev->driver)); + rk30_lcdc_deinit(lcdc_dev); + iounmap(lcdc_dev->reg_vir_base); + release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); + kfree(lcdc_dev->screen); + kfree(lcdc_dev); + return 0; +} + +static void rk30_lcdc_shutdown(struct platform_device *pdev) +{ + struct rk30_lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + if(lcdc_dev->driver.cur_screen->standby) //standby the screen if necessary + lcdc_dev->driver.cur_screen->standby(1); + if(lcdc_dev->driver.screen_ctr_info->io_disable) //power off the screen if necessary + lcdc_dev->driver.screen_ctr_info->io_disable(); + if(lcdc_dev->driver.cur_screen->sscreen_set) //turn off lvds if necessary + lcdc_dev->driver.cur_screen->sscreen_set(lcdc_dev->driver.cur_screen , 0); + rk_fb_unregister(&(lcdc_dev->driver)); + rk30_lcdc_deinit(lcdc_dev); + /*iounmap(lcdc_dev->reg_vir_base); + release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len); + kfree(lcdc_dev->screen); + kfree(lcdc_dev);*/ +} + + +static struct platform_driver rk30lcdc_driver = { + .probe = rk30_lcdc_probe, + .remove = __devexit_p(rk30_lcdc_remove), + .driver = { + .name = "rk30-lcdc", + .owner = THIS_MODULE, + }, + .suspend = rk30_lcdc_suspend, + .resume = rk30_lcdc_resume, + .shutdown = rk30_lcdc_shutdown, +}; + +static int __init rk30_lcdc_module_init(void) +{ + return platform_driver_register(&rk30lcdc_driver); +} + +static void __exit rk30_lcdc_module_exit(void) +{ + platform_driver_unregister(&rk30lcdc_driver); +} + + + +fs_initcall(rk30_lcdc_module_init); +module_exit(rk30_lcdc_module_exit); + + + diff --git a/drivers/video/rockchip/lcdc/rk30_lcdc.h b/drivers/video/rockchip/lcdc/rk30_lcdc.h new file mode 100644 index 000000000000..9576ed54c59a --- /dev/null +++ b/drivers/video/rockchip/lcdc/rk30_lcdc.h @@ -0,0 +1,542 @@ +#ifndef RK30_LCDC_H_ +#define RK30_LCDC_H_ + +#include + +#define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk)) +#define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val) +#define LcdRdReg(inf, addr) (inf->preg->addr) +#define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk)) +#define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk)) +#define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk)) +#define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val)) +#define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb() + +/******************************************************************** +** ½á¹¹¶¨Òå * +********************************************************************/ +/* LCDCµÄ¼Ä´æÆ÷½á¹¹ */ + +typedef volatile struct tagLCDC_REG +{ + /* offset 0x00~0xc0 */ + unsigned int SYS_CTRL0; //0x00 system control register 0 + unsigned int SYS_CTRL1; //0x04 system control register 1 + unsigned int DSP_CTRL0; //0x08 display control register 0 + unsigned int DSP_CTRL1; //0x0c display control register 1 + unsigned int INT_STATUS; //0x10 Interrupt status register + unsigned int MCU_CTRL ; //0x14 MCU mode contol register + unsigned int BLEND_CTRL; //0x18 Blending control register + unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register + unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register + unsigned int WIN2_COLOR_KEY_CTRL; //0x24 Win2 blending control register + unsigned int WIN0_YRGB_MST0; //0x28 Win0 active YRGB memory start address0 + unsigned int WIN0_CBR_MST0; //0x2c Win0 active Cbr memory start address0 + unsigned int WIN0_YRGB_MST1; //0x30 Win0 active YRGB memory start address1 + unsigned int WIN0_CBR_MST1; //0x34 Win0 active Cbr memory start address1 + unsigned int WIN0_VIR; //0x38 WIN0 virtual display width/height + unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height + unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel + unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel + unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting + unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting + unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset + unsigned int WIN1_YRGB_MST; //0x54 Win1 active YRGB memory start address + unsigned int WIN1_CBR_MST; //0x58 Win1 active Cbr memory start address + unsigned int WIN1_VIR; //0x5c WIN1 virtual display width/height + unsigned int WIN1_ACT_INFO; //0x60 Win1 active window width/height + unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel + unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel + unsigned int WIN1_SCL_FACTOR_YRGB; //0x6c Win1 YRGB scaling factor setting + unsigned int WIN1_SCL_FACTOR_CBR; //0x70 Win1 YRGB scaling factor setting + unsigned int WIN1_SCL_OFFSET; //0x74 Win1 Cbr scaling start point offset + unsigned int WIN2_MST; //0x78 win2 memort start address + unsigned int WIN2_VIR; //0x7c win2 virtual stride + unsigned int WIN2_DSP_INFO; //0x80 Win2 display width/height on panel + unsigned int WIN2_DSP_ST; //0x84 Win2 display start point on panel + unsigned int HWC_MST; //0x88 HWC memory start address + unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel + unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0 + unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1 + unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2 + unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point + unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point + unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point + unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point + unsigned int DSP_VS_ST_END_F1; //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode + unsigned int DSP_VACT_ST_END_F1; //0xb0 Vertical scanning active start/end point of even filed in interlace mode + unsigned int reserved0[(0xc0-0xb4)/4]; + unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH + unsigned int reserved1[(0x100-0xc4)/4]; + unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port + unsigned int reserved2[(0x200-0x104)/4]; + unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port + unsigned int reserved3[(0x400-0x204)/4]; + unsigned int WIN2_LUT_ADDR; + unsigned int reserved4[(0x800-0x404)/4]; + unsigned int DSP_LUT_ADDR; + +} LCDC_REG, *pLCDC_REG; + + +/* SYS_CONFIG */ + +#define m_LCDC_DMA_STOP (1<<0) +#define m_LCDC_STANDBY (1<<1) +#define m_HWC_RELOAD_EN (1<<2) +#define m_W0_AXI_OUTSTANDING_DISABLE (1<<3) +#define m_W1_AXI_OUTSTANDING_DISABLE (1<<4) +#define m_W2_AXI_OUTSTANDING_DISABLE (1<<5) +#define m_DMA_BURST_LENGTH (3<<6) +#define m_WIN0_YRGB_CHANNEL0_ID ((0x07)<<8) +#define m_WIN0_CBR_CHANNEL0_ID ((0x07)<<11) +#define m_WIN0_YRGB_CHANNEL1_ID ((0x07)<<14) +#define m_WIN0_CBR_CHANNEL1_ID ((0x07)<<17) +#define m_WIN1_YRGB_CHANNEL_ID ((0x07)<<20) +#define m_WIN1_CBR_CHANNEL_ID ((0x07)<<23) +#define m_WIN2_CHANNEL_ID ((0x07)<<26) +#define m_HWC_CHANNEL_ID ((0x07)<<29) + + + + + +#define v_LCDC_DMA_STOP(x) (((x)&1)<<0) +#define v_LCDC_STANDBY(x) (((x)&1)<<1) +#define v_HWC_RELOAD_EN(x) (((x)&1)<<2) +#define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3) +#define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4) +#define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5) +#define v_DMA_BURST_LENGTH(x) (((x)&3)<<6) +#define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8) +#define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11) +#define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14) +#define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17) +#define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20) +#define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23) +#define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26) +#define v_HWC_CHANNEL_ID(x) (((x)&7)<<29) + + + +//LCDC_SYS_CTRL1 +#define m_W0_EN (1<<0) +#define m_W1_EN (1<<1) +#define m_W2_EN (1<<2) +#define m_HWC_EN (1<<3) +#define m_W0_FORMAT (7<<4) +#define m_W1_FORMAT (7<<7) +#define m_W2_FORMAT (7<<10) +#define m_HWC_COLOR_MODE (1<<13) +#define m_HWC_SIZE_SELET (1<<14) +#define m_W0_3D_MODE_EN (1<<15) +#define m_W0_3D_MODE_SELET (7<<16) +#define m_W0_RGB_RB_SWAP (1<<19) +#define m_W0_RGB_ALPHA_SWAP (1<<20) +#define m_W0_YRGB_M8_SWAP (1<<21) +#define m_W0_CBCR_SWAP (1<<22) +#define m_W1_RGB_RB_SWAP (1<<23) +#define m_W1_RGB_ALPHA_SWAP (1<<24) +#define m_W1_YRGB_M8_SWAP (1<<25) +#define m_W1_CBCR_SWAP (1<<26) +#define m_W2_RGB_RB_SWAP (1<<27) +#define m_W2_RGB_ALPHA_SWAP (1<<28) +#define m_W2_8pp_PALETTE_ENDIAN_SELECT (1<<29) +#define m_W2_LUT_RAM_EN (1<<30) +#define m_DSP_LUT_RAM_EN (1<<31) + +#define v_W0_EN(x) (((x)&1)<<0) +#define v_W1_EN(x) (((x)&1)<<1) +#define v_W2_EN(x) (((x)&1)<<2) +#define v_HWC_EN(x) (((x)&1)<<3) +#define v_W0_FORMAT(x) (((x)&7)<<4) +#define v_W1_FORMAT(x) (((x)&7)<<7) +#define v_W2_FORMAT(x) (((x)&7)<<10) +#define v_HWC_COLOR_MODE(x) (((x)&1)<<13) +#define v_HWC_SIZE_SELET(x) (((x)&1)<<14) +#define v_W0_3D_MODE_EN(x) (((x)&1)<<15) +#define v_W0_3D_MODE_SELET(x) (((x)&3)<<16) +#define v_W0_RGB_RB_SWAP(x) (((x)&1)<<19) +#define v_W0_RGB_ALPHA_SWAP(x) (((x)&1)<<20) +#define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<21) +#define v_W0_CBCR_SWAP(x) (((x)&1)<<22) +#define v_W1_RGB_RB_SWAP(x) (((x)&1)<<23) +#define v_W1_RGB_ALPHA_SWAP(x) (((x)&1)<<24) +#define v_W1_YRGB_M8_SWAP(x) (((x)&1)<<25) +#define v_W1_CBCR_SWAP(x) (((x)&1)<<26) +#define v_W2_RGB_RB_SWAP(x) (((x)&1)<<27) +#define v_W2_RGB_ALPHA_SWAP(x) (((x)&1)<<28) +#define v_W2_8pp_PALETTE_ENDIAN_SELECT (((x)&1)<<29) +#define v_W2_LUT_RAM_EN(x) (((x)&1)<<30) +#define v_DSP_LUT_RAM_EN(x) (((x)&1)<<31) + +//LCDC_DSP_CTRL_REG0 +#define m_DISPLAY_FORMAT (0x0f<<0) +#define m_HSYNC_POLARITY (1<<4) +#define m_VSYNC_POLARITY (1<<5) +#define m_DEN_POLARITY (1<<6) +#define m_DCLK_POLARITY (1<<7) +#define m_W0W1_POSITION_SWAP (1<<8) +#define m_DITHER_UP_EN (1<<9) +#define m_DITHER_DOWN_MODE (1<<10) +#define m_DITHER_DOWN_EN (1<<11) +#define m_INTERLACE_DSP_EN (1<<12) +#define m_INTERLACE_FIELD_POLARITY (1<<13) +#define m_W0_INTERLACE_READ_MODE (1<<14) +#define m_W1_INTERLACE_READ_MODE (1<<15) +#define m_W2_INTERLACE_READ_MODE (1<<16) +#define m_W0_YRGB_DEFLICK_MODE (1<<17) +#define m_W0_CBR_DEFLICK_MODE (1<<18) +#define m_W1_YRGB_DEFLICK_MODE (1<<19) +#define m_W1_CBR_DEFLICK_MODE (1<<20) +#define m_W0_ALPHA_MODE (1<<21) +#define m_W1_ALPHA_MODE (1<<22) +#define m_W2_ALPHA_MODE (1<<23) +#define m_W0_COLOR_SPACE_CONVERSION (3<<24) +#define m_W1_COLOR_SPACE_CONVERSION (3<<26) +#define m_W2_COLOR_SPACE_CONVERSION (1<<28) +#define m_YCRCB_CLIP_EN (1<<29) +#define m_CBR_FILTER_656 (1<<30) +#define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) //eanble for low power + +#define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0) +#define v_HSYNC_POLARITY(x) (((x)&1)<<4) +#define v_VSYNC_POLARITY(x) (((x)&1)<<5) +#define v_DEN_POLARITY(x) (((x)&1)<<6) +#define v_DCLK_POLARITY(x) (((x)&1)<<7) +#define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8) +#define v_DITHER_UP_EN(x) (((x)&1)<<9) +#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10) +#define v_DITHER_DOWN_EN(x) (((x)&1)<<11) +#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12) +#define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13) +#define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14) +#define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15) +#define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16) +#define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17) +#define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18) +#define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19) +#define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20) +#define v_W0_ALPHA_MODE(x) (((x)&1)<<21) +#define v_W1_ALPHA_MODE(x) (((x)&1)<<22) +#define v_W2_ALPHA_MODE(x) (((x)&1)<<23) +#define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24) +#define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26) +#define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28) +#define v_YCRCB_CLIP_EN(x) (((x)&1)<<29) +#define v_CBR_FILTER_656(x) (((x)&1)<<30) +#define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) //eanble for low power + +//LCDC_DSP_CTRL_REG1 +#define m_BG_COLOR (0xffffff<<0) +#define m_BG_B (0xff<<0) +#define m_BG_G (0xff<<8) +#define m_BG_R (0xff<<16) +#define m_BLANK_MODE (1<<24) +#define m_BLACK_MODE (1<<25) +#define m_OUTPUT_BG_SWAP (1<<26) +#define m_OUTPUT_RB_SWAP (1<<27) +#define m_OUTPUT_RG_SWAP (1<<28) +#define m_DELTA_SWAP (1<<29) +#define m_DUMMY_SWAP (1<<30) + +#define v_BG_COLOR(x) (((x)&0xffffff)<<0) +#define v_BG_B(x) (((x)&0xff)<<0) +#define v_BG_G(x) (((x)&0xff)<<8) +#define v_BG_R(x) (((x)&0xff)<<16) +#define v_BLANK_MODE(x) (((x)&1)<<24) +#define v_BLACK_MODE(x) (((x)&1)<<25) +#define v_OUTPUT_BG_SWAP(x) (((x)&1)<<26) +#define v_OUTPUT_RB_SWAP(x) (((x)&1)<<27) +#define v_OUTPUT_RG_SWAP(x) (((x)&1)<<28) +#define v_DELTA_SWAP(x) (((x)&1)<<29) +#define v_DUMMY_SWAP(x) (((x)&1)<<30) + + +//LCDC_INT_STATUS +#define v_HOR_START_INT_STA (1<<0) //status +#define v_FRM_START_INT_STA (1<<1) +#define v_LINE_FLAG_INT_STA (1<<2) +#define v_BUS_ERR_INT_STA (1<<3) +#define m_HOR_START_INT_EN (1<<4) //enable +#define m_FRM_START_INT_EN (1<<5) +#define m_LINE_FLAG_INT_EN (1<<6) +#define m_BUS_ERR_INT_EN (1<<7) +#define m_HOR_START_INT_CLEAR (1<<8) //auto clear +#define m_FRM_START_INT_CLEAR (1<<9) +#define m_LINE_FLAG_INT_CLEAR (1<<10) +#define m_BUS_ERR_INT_CLEAR (1<<11) +#define m_LINE_FLAG_NUM (0xfff<<12) +#define v_HOR_START_INT_EN(x) (((x)&1)<<4) +#define v_FRM_START_INT_EN(x) (((x)&1)<<5) +#define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6) +#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7) +#define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8) +#define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9) +#define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10) +#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11) +#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) + + + +//LCDC_MCU_TIMING_CTRL +#define m_MCU_WRITE_PERIOD (0x3f<<0) +#define m_MCU_CS_ST (0xf<<6) +#define m_MCU_CS_END (0x3f<<10) +#define m_MCU_RW_ST (0xf<<16) +#define m_MCU_RW_END (0x3f<<20) +#define m_MCU_BPS_CLK_SEL (1<<26) +#define m_MCU_HOLDMODE_SELECT (1<<27) +#define m_MCU_HOLDMODE_FRAME_ST (1<<28) +#define m_MCU_RS_SELECT (1<<29) +#define m_MCU_BYPASSMODE_SELECT (1<<30) +#define m_MCU_OUTPUT_SELECT (1<<31) +#define v_MCU_WRITE_PERIOD(x) (((x)&0x3f)<<0) +#define v_MCU_CS_ST(x) (((x)&0xf)<<6) +#define v_MCU_CS_END(x) (((x)&0x3f)<<10) +#define v_MCU_RW_ST(x) (((x)&0xf)<<16) +#define v_MCU_RW_END(x) (((x)&0x3f)<<20) +#define v_MCU_BPS_CLK_SEL (((x)&1)<<26) +#define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27) +#define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28) +#define v_MCU_RS_SELECT(x) (((x)&1)<<29) +#define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30) +#define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31) + +//LCDC_ BLEND_CTRL +#define m_HWC_BLEND_EN (1<<0) +#define m_W2_BLEND_EN (1<<1) +#define m_W1_BLEND_EN (1<<2) +#define m_W0_BLEND_EN (1<<3) +#define m_HWC_BLEND_FACTOR (15<<4) +#define m_W2_BLEND_FACTOR (0xff<<8) +#define m_W1_BLEND_FACTOR (0xff<<16) +#define m_W0_BLEND_FACTOR (0xff<<24) + +#define v_HWC_BLEND_EN(x) (((x)&1)<<0) +#define v_W2_BLEND_EN(x) (((x)&1)<<1) +#define v_W1_BLEND_EN(x) (((x)&1)<<2) +#define v_W0_BLEND_EN(x) (((x)&1)<<3) +#define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4) +#define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8) +#define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16) +#define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24) + + +//LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL +#define m_KEYCOLOR (0xffffff<<0) +#define m_KEYCOLOR_B (0xff<<0) +#define m_KEYCOLOR_G (0xff<<8) +#define m_KEYCOLOR_R (0xff<<16) +#define m_COLORKEY_EN (1<<24) +#define v_KEYCOLOR(x) (((x)&0xffffff)<<0) +#define v_KEYCOLOR_B(x) (((x)&0xff)<<0) +#define v_KEYCOLOR_G(x) (((x)&0xff)<<8) +#define v_KEYCOLOR_R(x) (((x)&0xff)<<16) +#define v_COLORKEY_EN(x) (((x)&1)<<24) + +//LCDC_DEFLICKER_SCL_OFFSET +#define m_W0_YRGB_VSD_OFFSET (0xff<<0) +#define m_W0_YRGB_VSP_OFFSET (0xff<<8) +#define m_W1_VSD_OFFSET (0xff<<16) +#define m_W1_VSP_OFFSET (0xff<<24) +#define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0) +#define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8) +#define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16) +#define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24) + + + + + +//AXI MS ID +#define m_W0_YRGB_CH_ID (0xF<<0) +#define m_W0_CBR_CH_ID (0xF<<4) +#define m_W1_YRGB_CH_ID (0xF<<8) +#define m_W2_CH_ID (0xF<<12) +#define m_HWC_CH_ID (0xF<<16) +#define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0) +#define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4) +#define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8) +#define v_W2_CH_ID(x) (((x)&0xF)<<12) +#define v_HWC_CH_ID(x) (((x)&0xF)<<16) + + +/* Low Bits Mask */ +#define m_WORDLO (0xffff<<0) +#define m_WORDHI (0xffff<<16) +#define v_WORDLO(x) (((x)&0xffff)<<0) +#define v_WORDHI(x) (((x)&0xffff)<<16) + + +//LCDC_WINx_SCL_FACTOR_Y/CBCR +#define v_X_SCL_FACTOR(x) ((x)<<0) +#define v_Y_SCL_FACTOR(x) ((x)<<16) + +//LCDC_DSP_HTOTAL_HS_END +#define v_HSYNC(x) ((x)<<0) //hsync pulse width +#define v_HORPRD(x) ((x)<<16) //horizontal period + + +//LCDC_DSP_HACT_ST_END +#define v_HAEP(x) ((x)<<0) //horizontal active end point +#define v_HASP(x) ((x)<<16) //horizontal active start point + +//LCDC_DSP_VTOTAL_VS_END +#define v_VSYNC(x) ((x)<<0) +#define v_VERPRD(x) ((x)<<16) + +//LCDC_DSP_VACT_ST_END +#define v_VAEP(x) ((x)<<0) +#define v_VASP(x) ((x)<<16) + + +//LCDC_WINx_VIR ,x is number of words of win0 virtual width +#define v_ARGB888_VIRWIDTH(x) (x) +#define v_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3)) +#define v_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0)) +#define v_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0)) + +#define m_ACTWIDTH (0xffff<<0) +#define m_ACTHEIGHT (0xffff<<16) +#define v_ACTWIDTH(x) (((x)&0xffff)<<0) +#define v_ACTHEIGHT(x) (((x)&0xffff)<<16) + +#define m_VIRST_X (0xffff<<0) +#define m_VIRST_Y (0xffff<<16) +#define v_VIRST_X(x) (((x)&0xffff)<<0) +#define v_VIRST_Y(x) (((x)&0xffff)<<16) + +#define m_PANELST_X (0x3ff<<0) +#define m_PANELST_Y (0x3ff<<16) +#define v_PANELST_X(x) (((x)&0x3ff)<<0) +#define v_PANELST_Y(x) (((x)&0x3ff)<<16) + +#define m_PANELWIDTH (0x3ff<<0) +#define m_PANELHEIGHT (0x3ff<<16) +#define v_PANELWIDTH(x) (((x)&0x3ff)<<0) +#define v_PANELHEIGHT(x) (((x)&0x3ff)<<16) + +#define m_HWC_B (0xff<<0) +#define m_HWC_G (0xff<<8) +#define m_HWC_R (0xff<<16) +#define m_W0_YRGB_HSP_OFFSET (0xff<<24) +#define m_W0_YRGB_HSD_OFFSET (0xff<<24) +#define v_HWC_B(x) (((x)&0xff)<<0) +#define v_HWC_G(x) (((x)&0xff)<<8) +#define v_HWC_R(x) (((x)&0xff)<<16) +#define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24) +#define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24) + +//LCDC_WIN0_ACT_INFO +#define v_ACT_WIDTH(x) ((x-1)<<0) +#define v_ACT_HEIGHT(x) ((x-1)<<16) + +//LCDC_WIN0_DSP_INFO +#define v_DSP_WIDTH(x) ((x-1)<<0) +#define v_DSP_HEIGHT(x) ((x-1)<<16) + +//LCDC_WIN0_DSP_ST //x,y start point of the panel scanning +#define v_DSP_STX(x) (x<<0) +#define v_DSP_STY(x) (x<<16) + +//Panel display scanning +#define m_PANEL_HSYNC_WIDTH (0x3ff<<0) +#define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16) +#define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0) +#define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16) + +#define m_PANEL_END (0x3ff<<0) +#define m_PANEL_START (0x3ff<<16) +#define v_PANEL_END(x) (((x)&0x3ff)<<0) +#define v_PANEL_START(x) (((x)&0x3ff)<<16) + +#define m_PANEL_VSYNC_WIDTH (0x3ff<<0) +#define m_PANEL_VERTICAL_PERIOD (0x3ff<<16) +#define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0) +#define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16) +//----------- + +#define m_HSCALE_FACTOR (0xffff<<0) +#define m_VSCALE_FACTOR (0xffff<<16) +#define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0) +#define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16) + +#define m_W0_CBR_HSD_OFFSET (0xff<<0) +#define m_W0_CBR_HSP_OFFSET (0xff<<8) +#define m_W0_CBR_VSD_OFFSET (0xff<<16) +#define m_W0_CBR_VSP_OFFSET (0xff<<24) +#define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0) +#define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8) +#define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16) +#define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24) + + + +#define CalScale(x, y) (((u32)x*0x1000)/y) +struct rk30_lcdc_device{ + int id; + struct rk_lcdc_device_driver driver; + rk_screen *screen; + + LCDC_REG *preg; // LCDC reg base address and backup reg + LCDC_REG regbak; + int __iomem *dsp_lut_addr_base; + + void __iomem *reg_vir_base; // virtual basic address of lcdc register + u32 reg_phy_base; // physical basic address of lcdc register + u32 len; // physical map length of lcdc register + spinlock_t reg_lock; //one time only one process allowed to config the register + bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed + u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc + + unsigned int irq; + + struct clk *pd; //lcdc power domain + struct clk *hclk; //lcdc AHP clk + struct clk *dclk; //lcdc dclk + struct clk *aclk; //lcdc share memory frequency + struct clk *aclk_parent; //lcdc aclk divider frequency source + struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable. + struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable. + struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable. + struct clk *pd_display; // display power domain + u32 pixclock; +}; + +struct lcdc_info{ +/*LCD CLK*/ + struct rk30_lcdc_device lcdc0; + struct rk30_lcdc_device lcdc1; + +}; + + +struct win_set { + volatile u32 y_offset; + volatile u32 c_offset; +}; + +struct win0_par { + u32 refcount; + u32 pseudo_pal[16]; + u32 y_offset; + u32 c_offset; + u32 xpos; //size in panel + u32 ypos; + u32 xsize; //start point in panel + u32 ysize; + enum data_format format; + + wait_queue_head_t wait; + struct win_set mirror; + struct win_set displ; + struct win_set done; + + u8 par_seted; + u8 addr_seted; +}; + +#endif + +