From: Chris Lattner Date: Fri, 14 Sep 2001 03:46:34 +0000 (+0000) Subject: Move the contents of the CodeGen/TargetMachine/Sparc directory to Target/Sparc X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1fddfd18abde2578a487bb247110acfd2226d62b;p=oota-llvm.git Move the contents of the CodeGen/TargetMachine/Sparc directory to Target/Sparc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@560 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/TargetMachine/Sparc/Makefile b/lib/CodeGen/TargetMachine/Sparc/Makefile deleted file mode 100644 index 2daca1f7729..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -LEVEL = ../../../.. - -DIRS = - -LIBRARYNAME = sparc - -## List source files in link order -Source = \ - Sparc.o \ - Sparc.burm.o \ - SparcInstrSelection.o - -include $(LEVEL)/Makefile.common - diff --git a/lib/CodeGen/TargetMachine/Sparc/Sparc.burg b/lib/CodeGen/TargetMachine/Sparc/Sparc.burg deleted file mode 100644 index 14e122c597c..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/Sparc.burg +++ /dev/null @@ -1,286 +0,0 @@ -%{ // -*- C++ -*- -#include -#include - //#include - -typedef InstrTreeNode* NODEPTR_TYPE; -#define OP_LABEL(p) ((p)->opLabel) -#define LEFT_CHILD(p) ((p)->LeftChild) -#define RIGHT_CHILD(p) ((p)->RightChild) -#define STATE_LABEL(p) ((p)->state) -#define PANIC printf -%} - -%start stmt - -%term Ret=1 /* return void from a function */ -%term RetValue=101 /* return a value from a function */ -%term BrUncond=2 -%term BrCond=102 -%term Switch=3 - /* 4 is unused */ -%term Not=4 -%term Add=5 -%term Sub=6 -%term Mul=7 -%term Div=8 -%term Rem=9 -%term And=10 -%term Or=11 -%term Xor=12 -%term SetCC=113 /* use this to match all SetCC instructions */ - /* %term SetEQ=13 */ - /* %term SetNE=14 */ - /* %term SetLE=15 */ - /* %term SetGE=16 */ - /* %term SetLT=17 */ - /* %term SetGT=18 */ -%term Malloc=19 -%term Free=20 -%term Alloca=21 -%term AllocaN=121 /* alloca with arg N */ -%term Load=22 -%term LoadIdx=122 /* load with index vector */ -%term Store=23 -%term GetElemPtr=24 -%term GetElemPtrIdx=124 /* getElemPtr with index vector */ - -%term Phi=25 - -%term Cast=26 /* cast that will be ignored. others are made explicit */ -%term ToBoolTy=126 -%term ToUByteTy=127 -%term ToSByteTy=128 -%term ToUShortTy=129 -%term ToShortTy=130 -%term ToUIntTy=131 -%term ToIntTy=132 -%term ToULongTy=133 -%term ToLongTy=134 -%term ToFloatTy=135 -%term ToDoubleTy=136 -%term ToArrayTy=137 -%term ToPointerTy=138 - -%term Call=27 -%term Shl=28 -%term Shr=29 - /* 30...46 are unused */ - /* - * The foll. values should match the constants in InstrForest.h - */ -%term VRegList=97 -%term VReg=98 -%term Constant=99 -%term Label=100 - /* 50+i is a variant of i, as defined above */ - - -%% -/*-----------------------------------------------------------------------* - * The productions of the grammar. - * Note that all chain rules are numbered 101 and above. - * Also, a special case of production X is numbered 100+X, 200+X, etc. - * The cost of a 1-cycle operation is represented as 10, to allow - * finer comparisons of costs (effectively, fractions of 1/10). - *-----------------------------------------------------------------------*/ - - /* - * The top-level statements - */ -stmt: Ret = 1 (30); -stmt: RetValue(reg) = 2 (30); -stmt: Store(reg,reg) = 3 (10); -stmt: Store(reg,ptrreg) = 4 (10); -stmt: BrUncond = 5 (20); -stmt: BrCond(boolconst) = 6 (10); /* may save one instruction */ -stmt: BrCond(bool) = 7 (20); -stmt: BrCond(boolreg) = 8 (20); -stmt: Switch(reg) = 9 (30); /* cost = load + branch */ - -stmt: reg = 111 (0); -stmt: boolconst = 112 (0); -stmt: bool = 113 (0); - - /* - * List node used for nodes with more than 2 children - */ -reg: VRegList(reg,reg) = 10 (0); - - /* - * The unary operators. We encode NOT and individual casts into - * separate non-terminals to combine instructions for some cases: - * Eg1: zdouble <- todouble(xfloat) * todouble(yfloat) - * Eg2: c <- a AND (NOT b). - * Note that the costs are counted for the individual non-terminals - * below, not for reg. - */ -reg: not = 121 (0); -reg: tobool = 122 (0); -reg: toubyte = 123 (0); -reg: tosbyte = 124 (0); -reg: toushort = 125 (0); -reg: toshort = 126 (0); -reg: touint = 127 (0); -reg: toint = 128 (0); -reg: toulong = 129 (0); -reg: tolong = 130 (0); -reg: tofloat = 131 (0); -reg: todouble = 132 (0); -reg: todoubleConst = 133 (0); - -not: Not(reg) = 21 (10); -tobool: ToBoolTy(reg) = 22 (10); -toubyte: ToUByteTy(reg) = 23 (10); -tosbyte: ToSByteTy(reg) = 24 (10); -toushort: ToUShortTy(reg) = 25 (10); -toshort: ToShortTy(reg) = 26 (10); -touint: ToUIntTy(reg) = 27 (10); -toint: ToIntTy(reg) = 28 (10); -toulong: ToULongTy(reg) = 29 (10); -tolong: ToLongTy(reg) = 30 (10); -tofloat: ToFloatTy(reg) = 31 (10); -todouble: ToDoubleTy(reg) = 32 (10); -todoubleConst: ToDoubleTy(Constant) = 232 (10); - -reg: ToArrayTy(reg) = 19 (10); -reg: ToPointerTy(reg) = 20 (10); - - /* - * The binary operators. - */ -reg: Add(reg,reg) = 33 (10); -reg: Sub(reg,reg) = 34 (10); -reg: Mul(reg,reg) = 35 (30); -reg: Mul(todouble,todouble) = 135 (20); /* avoids 1-2 type converts */ -reg: Div(reg,reg) = 36 (60); -reg: Rem(reg,reg) = 37 (60); -reg: And(reg,reg) = 38 (10); -reg: And(reg,not) = 138 (0); /* cost is counted for not */ -reg: Or (reg,reg) = 39 (10); -reg: Or (reg,not) = 139 (0); /* cost is counted for not */ -reg: Xor(reg,reg) = 40 (10); -reg: Xor(reg,not) = 140 (0); /* cost is counted for not */ - - /* - * The binary operators with one constant argument. - * We do not need the not(Constant) case because - * constant folding should take care of that beforehand. - */ -reg: Add(reg,Constant) = 233 (10); -reg: Sub(reg,Constant) = 234 (10); -reg: Mul(reg,Constant) = 235 (30); -reg: Mul(todouble,todoubleConst) = 335 (20); /* avoids 1-2 type converts */ -reg: Div(reg,Constant) = 236 (60); -reg: Rem(reg,Constant) = 237 (60); -reg: And(reg,Constant) = 238 (10); -reg: Or (reg,Constant) = 239 (10); -reg: Xor(reg,Constant) = 240 (10); - - /* - * The SetCC instructions and other boolean values - */ -boolconst: SetCC(reg,Constant) = 41 (10); -bool: SetCC(reg,reg) = 42 (10); -boolreg: VReg = 43 (0); -boolreg: Constant = 44 (0); - - /* - * Memory access instructions - */ -reg: Load(reg) = 51 (30); -reg: Load(ptrreg) = 52 (20); /* 1 counted for ptrreg */ -reg: LoadIdx(reg,reg) = 53 (30); -reg: LoadIdx(ptrreg,reg) = 54 (20); /* 1 counted for ptrreg */ -reg: ptrreg = 155 (0); -ptrreg: GetElemPtr(reg) = 55 (10); -ptrreg: GetElemPtrIdx(reg,reg) = 56 (10); -reg: Alloca = 57 (10); -reg: AllocaN(reg) = 58 (10); - - /* - * Other operators producing register values - */ -reg: Call = 61 (0); -reg: Shl(reg,reg) = 62 (20); /* 1 for issue restrictions */ -reg: Shr(reg,reg) = 63 (20); /* 1 for issue restrictions */ -reg: Phi(reg,reg) = 64 (0); - - /* - * Finally, leaf nodes of expression trees (other than boolreg) - */ -reg: VReg = 71 (0); -reg: Constant = 72 (3); /* prefer direct use */ - - - -%% -/*-----------------------------------------------------------------------* - * The rest of this file provides code to print the cover produced - * by BURG and information about computed tree cost and matches. - * This code was taken from sample.gr provided with BURG. - *-----------------------------------------------------------------------*/ - -void printcover(NODEPTR_TYPE p, int goalnt, int indent) { - int eruleno = burm_rule(STATE_LABEL(p), goalnt); - short *nts = burm_nts[eruleno]; - NODEPTR_TYPE kids[10]; - int i; - - if (eruleno == 0) { - printf("no cover\n"); - return; - } - for (i = 0; i < indent; i++) - printf("."); - printf("%s\n", burm_string[eruleno]); - burm_kids(p, eruleno, kids); - for (i = 0; nts[i]; i++) - printcover(kids[i], nts[i], indent+1); -} - -void printtree(NODEPTR_TYPE p) { - int op = burm_op_label(p); - - printf("%s", burm_opname[op]); - switch (burm_arity[op]) { - case 0: - break; - case 1: - printf("("); - printtree(burm_child(p, 0)); - printf(")"); - break; - case 2: - printf("("); - printtree(burm_child(p, 0)); - printf(", "); - printtree(burm_child(p, 1)); - printf(")"); - break; - } -} - -int treecost(NODEPTR_TYPE p, int goalnt, int costindex) { - int eruleno = burm_rule(STATE_LABEL(p), goalnt); - int cost = burm_cost[eruleno][costindex], i; - short *nts = burm_nts[eruleno]; - NODEPTR_TYPE kids[10]; - - burm_kids(p, eruleno, kids); - for (i = 0; nts[i]; i++) - cost += treecost(kids[i], nts[i], costindex); - return cost; -} - -void printMatches(NODEPTR_TYPE p) { - int nt; - int eruleno; - - printf("Node 0x%lx= ", (unsigned long)p); - printtree(p); - printf(" matched rules:\n"); - for (nt = 1; burm_ntname[nt] != (char*)NULL; nt++) - if ((eruleno = burm_rule(STATE_LABEL(p), nt)) != 0) - printf("\t%s\n", burm_string[eruleno]); -} diff --git a/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp b/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp deleted file mode 100644 index 017749f1107..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp +++ /dev/null @@ -1,126 +0,0 @@ -//*************************************************************************** -// File: -// Sparc.cpp -// -// Purpose: -// -// History: -// 7/15/01 - Vikram Adve - Created -//**************************************************************************/ - -#include "SparcInternals.h" -#include "llvm/Method.h" -#include "llvm/CodeGen/InstrScheduling.h" -#include "llvm/CodeGen/InstrSelection.h" - - - -//--------------------------------------------------------------------------- -// class UltraSparcInstrInfo -// -// Purpose: -// Information about individual instructions. -// Most information is stored in the SparcMachineInstrDesc array above. -// Other information is computed on demand, and most such functions -// default to member functions in base class MachineInstrInfo. -//--------------------------------------------------------------------------- - -/*ctor*/ -UltraSparcInstrInfo::UltraSparcInstrInfo() - : MachineInstrInfo(SparcMachineInstrDesc, - /*descSize = */ NUM_TOTAL_OPCODES, - /*numRealOpCodes = */ NUM_REAL_OPCODES) -{ -} - - -//--------------------------------------------------------------------------- -// class UltraSparcSchedInfo -// -// Purpose: -// Scheduling information for the UltraSPARC. -// Primarily just initializes machine-dependent parameters in -// class MachineSchedInfo. -//--------------------------------------------------------------------------- - -/*ctor*/ -UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii) - : MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES, - mii, - SparcRUsageDesc, - SparcInstrUsageDeltas, - SparcInstrIssueDeltas, - sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta), - sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta)) -{ - maxNumIssueTotal = 4; - longestIssueConflict = 0; // computed from issuesGaps[] - - branchMispredictPenalty = 4; // 4 for SPARC IIi - branchTargetUnknownPenalty = 2; // 2 for SPARC IIi - l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi - l1ICacheMissPenalty = 8; // ? for SPARC IIi - - inOrderLoads = true; // true for SPARC IIi - inOrderIssue = true; // true for SPARC IIi - inOrderExec = false; // false for most architectures - inOrderRetire= true; // true for most architectures - - // must be called after above parameters are initialized. - this->initializeResources(); -} - -void -UltraSparcSchedInfo::initializeResources() -{ - // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps - MachineSchedInfo::initializeResources(); - - // Machine-dependent fixups go here. None for now. -} - - -//--------------------------------------------------------------------------- -// class UltraSparcMachine -// -// Purpose: -// Primary interface to machine description for the UltraSPARC. -// Primarily just initializes machine-dependent parameters in -// class TargetMachine, and creates machine-dependent subclasses -// for classes such as MachineInstrInfo. -// -//--------------------------------------------------------------------------- - -UltraSparc::UltraSparc() - : TargetMachine("UltraSparc-Native") -{ - machineInstrInfo = new UltraSparcInstrInfo; - machineSchedInfo = new UltraSparcSchedInfo(machineInstrInfo); - - optSizeForSubWordData = 4; - minMemOpWordSize = 8; - maxAtomicMemOpWordSize = 8; - zeroRegNum = 0; // %g0 always gives 0 on Sparc -} - -UltraSparc::~UltraSparc() -{ - delete (UltraSparcInstrInfo*) machineInstrInfo; - delete (UltraSparcSchedInfo*) machineSchedInfo; -} - - -bool UltraSparc::compileMethod(Method *M) { - if (SelectInstructionsForMethod(M, *this)) { - cerr << "Instruction selection failed for method " << M->getName() - << "\n\n"; - return true; - } - - if (ScheduleInstructionsWithSSA(M, *this)) { - cerr << "Instruction scheduling before allocation failed for method " - << M->getName() << "\n\n"; - return true; - } - return false; -} diff --git a/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp b/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp deleted file mode 100644 index c73264c2210..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp +++ /dev/null @@ -1,2016 +0,0 @@ -//*************************************************************************** -// File: -// SparcInstrSelection.cpp -// -// Purpose: -// -// History: -// 7/02/01 - Vikram Adve - Created -//**************************************************************************/ - -#include "SparcInternals.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/InstrForest.h" -#include "llvm/CodeGen/InstrSelection.h" -#include "llvm/Support/MathExtras.h" -#include "llvm/DerivedTypes.h" -#include "llvm/iTerminators.h" -#include "llvm/iMemory.h" -#include "llvm/iOther.h" -#include "llvm/BasicBlock.h" -#include "llvm/Method.h" -#include "llvm/ConstPoolVals.h" - - -//******************** Internal Data Declarations ************************/ - -// to be used later -struct BranchPattern { - bool flipCondition; // should the sense of the test be reversed - BasicBlock* targetBB; // which basic block to branch to - MachineInstr* extraBranch; // if neither branch is fall-through, then this - // BA must be inserted after the cond'l one -}; - -//************************* Forward Declarations ***************************/ - - -static MachineOpCode ChooseBprInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseBccInstruction (const InstructionNode* instrNode, - bool& isFPBranch); - -static MachineOpCode ChooseBpccInstruction (const InstructionNode* instrNode, - const BinaryOperator* setCCInst); - -static MachineOpCode ChooseBFpccInstruction (const InstructionNode* instrNode, - const BinaryOperator* setCCInst); - -static MachineOpCode ChooseMovFpccInstruction(const InstructionNode*); - -static MachineOpCode ChooseMovpccAfterSub (const InstructionNode* instrNode, - bool& mustClearReg, - int& valueToMove); - -static MachineOpCode ChooseConvertToFloatInstr(const InstructionNode*, - const Type* opType); - -static MachineOpCode ChooseConvertToIntInstr(const InstructionNode* instrNode, - const Type* opType); - -static MachineOpCode ChooseAddInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseSubInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseFcmpInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseMulInstruction (const InstructionNode* instrNode, - bool checkCasts); - -static MachineOpCode ChooseDivInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseLoadInstruction (const Type* resultType); - -static MachineOpCode ChooseStoreInstruction (const Type* valueType); - -static void SetOperandsForMemInstr(MachineInstr* minstr, - const InstructionNode* vmInstrNode, - const TargetMachine& target); - -static void SetMemOperands_Internal (MachineInstr* minstr, - const InstructionNode* vmInstrNode, - Value* ptrVal, - Value* arrayOffsetVal, - const vector& idxVec, - const TargetMachine& target); - -static unsigned FixConstantOperands(const InstructionNode* vmInstrNode, - MachineInstr** mvec, - unsigned numInstr, - TargetMachine& target); - -static MachineInstr* MakeLoadConstInstr(Instruction* vmInstr, - Value* val, - TmpInstruction*& tmpReg, - MachineInstr*& getMinstr2); - -static void ForwardOperand (InstructionNode* treeNode, - InstructionNode* parent, - int operandNum); - - -//************************ Internal Functions ******************************/ - -// Convenience function to get the value of an integer constant, for an -// appropriate integer or non-integer type that can be held in an integer. -// The type of the argument must be the following: -// GetConstantValueAsSignedInt: any of the above, but the value -// must fit into a int64_t. -// -// isValidConstant is set to true if a valid constant was found. -// - -static int64_t GetConstantValueAsSignedInt(const Value *V, - bool &isValidConstant) { - if (!V->isConstant()) { isValidConstant = false; return 0; } - isValidConstant = true; - - if (V->getType() == Type::BoolTy) - return ((ConstPoolBool*)V)->getValue(); - if (V->getType()->isIntegral()) { - if (V->getType()->isSigned()) - return ((ConstPoolSInt*)V)->getValue(); - - assert(V->getType()->isUnsigned()); - uint64_t Val = ((ConstPoolUInt*)V)->getValue(); - - if (Val < INT64_MAX) // then safe to cast to signed - return (int64_t)Val; - } - - isValidConstant = false; - return 0; -} - - - -//------------------------------------------------------------------------ -// External Function: ThisIsAChainRule -// -// Purpose: -// Check if a given BURG rule is a chain rule. -//------------------------------------------------------------------------ - -extern bool -ThisIsAChainRule(int eruleno) -{ - switch(eruleno) - { - case 111: // stmt: reg - case 112: // stmt: boolconst - case 113: // stmt: bool - case 121: - case 122: - case 123: - case 124: - case 125: - case 126: - case 127: - case 128: - case 129: - case 130: - case 131: - case 132: - case 153: - case 155: return true; break; - - default: return false; break; - } -} - - -static inline MachineOpCode -ChooseBprInstruction(const InstructionNode* instrNode) -{ - MachineOpCode opCode; - - Instruction* setCCInstr = - ((InstructionNode*) instrNode->leftChild())->getInstruction(); - - switch(setCCInstr->getOpcode()) - { - case Instruction::SetEQ: opCode = BRZ; break; - case Instruction::SetNE: opCode = BRNZ; break; - case Instruction::SetLE: opCode = BRLEZ; break; - case Instruction::SetGE: opCode = BRGEZ; break; - case Instruction::SetLT: opCode = BRLZ; break; - case Instruction::SetGT: opCode = BRGZ; break; - default: - assert(0 && "Unrecognized VM instruction!"); - opCode = INVALID_OPCODE; - break; - } - - return opCode; -} - - -static inline MachineOpCode -ChooseBccInstruction(const InstructionNode* instrNode, - bool& isFPBranch) -{ - InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild(); - BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction(); - const Type* setCCType = setCCInstr->getOperand(0)->getType(); - - isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy); - - if (isFPBranch) - return ChooseBFpccInstruction(instrNode, setCCInstr); - else - return ChooseBpccInstruction(instrNode, setCCInstr); -} - - -static inline MachineOpCode -ChooseBpccInstruction(const InstructionNode* instrNode, - const BinaryOperator* setCCInstr) -{ - MachineOpCode opCode = INVALID_OPCODE; - - bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned(); - - if (isSigned) - { - switch(setCCInstr->getOpcode()) - { - case Instruction::SetEQ: opCode = BE; break; - case Instruction::SetNE: opCode = BNE; break; - case Instruction::SetLE: opCode = BLE; break; - case Instruction::SetGE: opCode = BGE; break; - case Instruction::SetLT: opCode = BL; break; - case Instruction::SetGT: opCode = BG; break; - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } - } - else - { - switch(setCCInstr->getOpcode()) - { - case Instruction::SetEQ: opCode = BE; break; - case Instruction::SetNE: opCode = BNE; break; - case Instruction::SetLE: opCode = BLEU; break; - case Instruction::SetGE: opCode = BCC; break; - case Instruction::SetLT: opCode = BCS; break; - case Instruction::SetGT: opCode = BGU; break; - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } - } - - return opCode; -} - -static inline MachineOpCode -ChooseBFpccInstruction(const InstructionNode* instrNode, - const BinaryOperator* setCCInstr) -{ - MachineOpCode opCode = INVALID_OPCODE; - - switch(setCCInstr->getOpcode()) - { - case Instruction::SetEQ: opCode = FBE; break; - case Instruction::SetNE: opCode = FBNE; break; - case Instruction::SetLE: opCode = FBLE; break; - case Instruction::SetGE: opCode = FBGE; break; - case Instruction::SetLT: opCode = FBL; break; - case Instruction::SetGT: opCode = FBG; break; - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } - - return opCode; -} - - -static inline MachineOpCode -ChooseMovFpccInstruction(const InstructionNode* instrNode) -{ - MachineOpCode opCode = INVALID_OPCODE; - - switch(instrNode->getInstruction()->getOpcode()) - { - case Instruction::SetEQ: opCode = MOVFE; break; - case Instruction::SetNE: opCode = MOVFNE; break; - case Instruction::SetLE: opCode = MOVFLE; break; - case Instruction::SetGE: opCode = MOVFGE; break; - case Instruction::SetLT: opCode = MOVFL; break; - case Instruction::SetGT: opCode = MOVFG; break; - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } - - return opCode; -} - - -// Assumes that SUBcc v1, v2 -> v3 has been executed. -// In most cases, we want to clear v3 and then follow it by instruction -// MOVcc 1 -> v3. -// Set mustClearReg=false if v3 need not be cleared before conditional move. -// Set valueToMove=0 if we want to conditionally move 0 instead of 1 -// (i.e., we want to test inverse of a condition) -// -// -static MachineOpCode -ChooseMovpccAfterSub(const InstructionNode* instrNode, - bool& mustClearReg, - int& valueToMove) -{ - MachineOpCode opCode = INVALID_OPCODE; - mustClearReg = true; - valueToMove = 1; - - switch(instrNode->getInstruction()->getOpcode()) - { - case Instruction::SetEQ: opCode = MOVNE; mustClearReg = false; - valueToMove = 0; break; - case Instruction::SetLE: opCode = MOVLE; break; - case Instruction::SetGE: opCode = MOVGE; break; - case Instruction::SetLT: opCode = MOVL; break; - case Instruction::SetGT: opCode = MOVG; break; - - case Instruction::SetNE: assert(0 && "No move required!"); - - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } - - return opCode; -} - - -static inline MachineOpCode -ChooseConvertToFloatInstr(const InstructionNode* instrNode, - const Type* opType) -{ - MachineOpCode opCode = INVALID_OPCODE; - - switch(instrNode->getOpLabel()) - { - case ToFloatTy: - if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy) - opCode = FITOS; - else if (opType == Type::LongTy) - opCode = FXTOS; - else if (opType == Type::DoubleTy) - opCode = FDTOS; - else if (opType == Type::FloatTy) - ; - else - assert(0 && "Cannot convert this type to FLOAT on SPARC"); - break; - - case ToDoubleTy: - if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy) - opCode = FITOD; - else if (opType == Type::LongTy) - opCode = FXTOD; - else if (opType == Type::FloatTy) - opCode = FSTOD; - else if (opType == Type::DoubleTy) - ; - else - assert(0 && "Cannot convert this type to DOUBLE on SPARC"); - break; - - default: - break; - } - - return opCode; -} - -static inline MachineOpCode -ChooseConvertToIntInstr(const InstructionNode* instrNode, - const Type* opType) -{ - MachineOpCode opCode = INVALID_OPCODE;; - - int instrType = (int) instrNode->getOpLabel(); - - if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy) - { - switch (opType->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FSTOI; break; - case Type::DoubleTyID: opCode = FDTOI; break; - default: - assert(0 && "Non-numeric non-bool type cannot be converted to Int"); - break; - } - } - else if (instrType == ToLongTy) - { - switch (opType->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FSTOX; break; - case Type::DoubleTyID: opCode = FDTOX; break; - default: - assert(0 && "Non-numeric non-bool type cannot be converted to Long"); - break; - } - } - else - assert(0 && "Should not get here, Mo!"); - - return opCode; -} - - -static inline MachineOpCode -ChooseAddInstruction(const InstructionNode* instrNode) -{ - MachineOpCode opCode = INVALID_OPCODE; - - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral() || - resultType->isPointerType() || - resultType->isMethodType() || - resultType->isLabelType()) - { - opCode = ADD; - } - else - { - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FADDS; break; - case Type::DoubleTyID: opCode = FADDD; break; - default: assert(0 && "Invalid type for ADD instruction"); break; - } - } - - return opCode; -} - - -static inline MachineInstr* -CreateMovFloatInstruction(const InstructionNode* instrNode, - const Type* resultType) -{ - MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy) - ? FMOVS : FMOVD); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - instrNode->getValue()); - return minstr; -} - -static inline MachineInstr* -CreateAddConstInstruction(const InstructionNode* instrNode) -{ - MachineInstr* minstr = NULL; - - Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); - - // Cases worth optimizing are: - // (1) Add with 0 for float or double: use an FMOV of appropriate type, - // instead of an FADD (1 vs 3 cycles). There is no integer MOV. - // - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType == Type::FloatTy || resultType == Type::DoubleTy) { - double dval = ((ConstPoolFP*) constOp)->getValue(); - if (dval == 0.0) - minstr = CreateMovFloatInstruction(instrNode, resultType); - } - - return minstr; -} - - -static inline MachineOpCode -ChooseSubInstruction(const InstructionNode* instrNode) -{ - MachineOpCode opCode = INVALID_OPCODE; - - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral() || - resultType->isPointerType()) - { - opCode = SUB; - } - else - { - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FSUBS; break; - case Type::DoubleTyID: opCode = FSUBD; break; - default: assert(0 && "Invalid type for SUB instruction"); break; - } - } - - return opCode; -} - - -static inline MachineInstr* -CreateSubConstInstruction(const InstructionNode* instrNode) -{ - MachineInstr* minstr = NULL; - - Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); - - // Cases worth optimizing are: - // (1) Sub with 0 for float or double: use an FMOV of appropriate type, - // instead of an FSUB (1 vs 3 cycles). There is no integer MOV. - // - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType == Type::FloatTy || - resultType == Type::DoubleTy) - { - double dval = ((ConstPoolFP*) constOp)->getValue(); - if (dval == 0.0) - minstr = CreateMovFloatInstruction(instrNode, resultType); - } - - return minstr; -} - - -static inline MachineOpCode -ChooseFcmpInstruction(const InstructionNode* instrNode) -{ - MachineOpCode opCode = INVALID_OPCODE; - - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) { - case Type::FloatTyID: opCode = FCMPS; break; - case Type::DoubleTyID: opCode = FCMPD; break; - default: assert(0 && "Invalid type for FCMP instruction"); break; - } - - return opCode; -} - - -// Assumes that leftArg and rightArg are both cast instructions. -// -static inline bool -BothFloatToDouble(const InstructionNode* instrNode) -{ - InstrTreeNode* leftArg = instrNode->leftChild(); - InstrTreeNode* rightArg = instrNode->rightChild(); - InstrTreeNode* leftArgArg = leftArg->leftChild(); - InstrTreeNode* rightArgArg = rightArg->leftChild(); - assert(leftArg->getValue()->getType() == rightArg->getValue()->getType()); - - // Check if both arguments are floats cast to double - return (leftArg->getValue()->getType() == Type::DoubleTy && - leftArgArg->getValue()->getType() == Type::FloatTy && - rightArgArg->getValue()->getType() == Type::FloatTy); -} - - -static inline MachineOpCode -ChooseMulInstruction(const InstructionNode* instrNode, - bool checkCasts) -{ - MachineOpCode opCode = INVALID_OPCODE; - - if (checkCasts && BothFloatToDouble(instrNode)) - { - return opCode = FSMULD; - } - // else fall through and use the regular multiply instructions - - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral()) - { - opCode = MULX; - } - else - { - switch(instrNode->leftChild()->getValue()->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FMULS; break; - case Type::DoubleTyID: opCode = FMULD; break; - default: assert(0 && "Invalid type for MUL instruction"); break; - } - } - - return opCode; -} - - -static inline MachineInstr* -CreateIntNegInstruction(Value* vreg) -{ - MachineInstr* minstr = new MachineInstr(SUB); - minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0); - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, vreg); - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, vreg); - return minstr; -} - - -static inline MachineInstr* -CreateMulConstInstruction(const InstructionNode* instrNode, - MachineInstr*& getMinstr2) -{ - MachineInstr* minstr = NULL; - getMinstr2 = NULL; - bool needNeg = false; - - Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); - - // Cases worth optimizing are: - // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV) - // (2) Multiply by 2^x for integer types: replace with Shift - // - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral()) - { - unsigned pow; - bool isValidConst; - int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst); - if (isValidConst) - { - bool needNeg = false; - if (C < 0) - { - needNeg = true; - C = -C; - } - - if (C == 0 || C == 1) - { - minstr = new MachineInstr(ADD); - - if (C == 0) - minstr->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0); - else - minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - } - else if (IsPowerOf2(C, pow)) - { - minstr = new MachineInstr((resultType == Type::LongTy) - ? SLLX : SLL); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed, - pow); - } - - if (minstr && needNeg) - { // insert after the instr to flip the sign - getMinstr2 = CreateIntNegInstruction(instrNode->getValue()); - } - } - } - else - { - if (resultType == Type::FloatTy || - resultType == Type::DoubleTy) - { - bool isValidConst; - double dval = ((ConstPoolFP*) constOp)->getValue(); - - if (isValidConst) - { - if (dval == 0) - { - minstr = new MachineInstr((resultType == Type::FloatTy) - ? FITOS : FITOD); - minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0); - } - else if (fabs(dval) == 1) - { - bool needNeg = (dval < 0); - - MachineOpCode opCode = needNeg - ? (resultType == Type::FloatTy? FNEGS : FNEGD) - : (resultType == Type::FloatTy? FMOVS : FMOVD); - - minstr = new MachineInstr(opCode); - minstr->SetMachineOperand(0, - MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - } - } - } - } - - if (minstr != NULL) - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - instrNode->getValue()); - - return minstr; -} - - -static inline MachineOpCode -ChooseDivInstruction(const InstructionNode* instrNode) -{ - MachineOpCode opCode = INVALID_OPCODE; - - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral()) - { - opCode = resultType->isSigned()? SDIVX : UDIVX; - } - else - { - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FDIVS; break; - case Type::DoubleTyID: opCode = FDIVD; break; - default: assert(0 && "Invalid type for DIV instruction"); break; - } - } - - return opCode; -} - - -static inline MachineInstr* -CreateDivConstInstruction(const InstructionNode* instrNode, - MachineInstr*& getMinstr2) -{ - MachineInstr* minstr = NULL; - getMinstr2 = NULL; - - Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); - - // Cases worth optimizing are: - // (1) Divide by 1 for any type: replace with copy (ADD or FMOV) - // (2) Divide by 2^x for integer types: replace with SR[L or A]{X} - // - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral()) - { - unsigned pow; - bool isValidConst; - int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst); - if (isValidConst) - { - bool needNeg = false; - if (C < 0) - { - needNeg = true; - C = -C; - } - - if (C == 1) - { - minstr = new MachineInstr(ADD); - minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - } - else if (IsPowerOf2(C, pow)) - { - MachineOpCode opCode= ((resultType->isSigned()) - ? (resultType==Type::LongTy)? SRAX : SRA - : (resultType==Type::LongTy)? SRLX : SRL); - minstr = new MachineInstr(opCode); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed, - pow); - } - - if (minstr && needNeg) - { // insert after the instr to flip the sign - getMinstr2 = CreateIntNegInstruction(instrNode->getValue()); - } - } - } - else - { - if (resultType == Type::FloatTy || - resultType == Type::DoubleTy) - { - bool isValidConst; - double dval = ((ConstPoolFP*) constOp)->getValue(); - - if (isValidConst && fabs(dval) == 1) - { - bool needNeg = (dval < 0); - - MachineOpCode opCode = needNeg - ? (resultType == Type::FloatTy? FNEGS : FNEGD) - : (resultType == Type::FloatTy? FMOVS : FMOVD); - - minstr = new MachineInstr(opCode); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - } - } - } - - if (minstr != NULL) - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - instrNode->getValue()); - - return minstr; -} - - -static inline MachineOpCode -ChooseLoadInstruction(const Type* resultType) -{ - MachineOpCode opCode = INVALID_OPCODE; - - switch (resultType->getPrimitiveID()) - { - case Type::BoolTyID: opCode = LDUB; break; - case Type::UByteTyID: opCode = LDUB; break; - case Type::SByteTyID: opCode = LDSB; break; - case Type::UShortTyID: opCode = LDUH; break; - case Type::ShortTyID: opCode = LDSH; break; - case Type::UIntTyID: opCode = LDUW; break; - case Type::IntTyID: opCode = LDSW; break; - case Type::ULongTyID: - case Type::LongTyID: opCode = LDX; break; - case Type::FloatTyID: opCode = LD; break; - case Type::DoubleTyID: opCode = LDD; break; - default: assert(0 && "Invalid type for Load instruction"); break; - } - - return opCode; -} - - -static inline MachineOpCode -ChooseStoreInstruction(const Type* valueType) -{ - MachineOpCode opCode = INVALID_OPCODE; - - switch (valueType->getPrimitiveID()) - { - case Type::BoolTyID: - case Type::UByteTyID: - case Type::SByteTyID: opCode = STB; break; - case Type::UShortTyID: - case Type::ShortTyID: opCode = STH; break; - case Type::UIntTyID: - case Type::IntTyID: opCode = STW; break; - case Type::ULongTyID: - case Type::LongTyID: opCode = STX; break; - case Type::FloatTyID: opCode = ST; break; - case Type::DoubleTyID: opCode = STD; break; - default: assert(0 && "Invalid type for Store instruction"); break; - } - - return opCode; -} - - -//------------------------------------------------------------------------ -// Function SetOperandsForMemInstr -// -// Choose addressing mode for the given load or store instruction. -// Use [reg+reg] if it is an indexed reference, and the index offset is -// not a constant or if it cannot fit in the offset field. -// Use [reg+offset] in all other cases. -// -// This assumes that all array refs are "lowered" to one of these forms: -// %x = load (subarray*) ptr, constant ; single constant offset -// %x = load (subarray*) ptr, offsetVal ; single non-constant offset -// Generally, this should happen via strength reduction + LICM. -// Also, strength reduction should take care of using the same register for -// the loop index variable and an array index, when that is profitable. -//------------------------------------------------------------------------ - -static void -SetOperandsForMemInstr(MachineInstr* minstr, - const InstructionNode* vmInstrNode, - const TargetMachine& target) -{ - MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction(); - - // Variables to hold the index vector, ptr value, and offset value. - // The major work here is to extract these for all 3 instruction types - // and then call the common function SetMemOperands_Internal(). - // - const vector* idxVec = & memInst->getIndexVec(); - vector* newIdxVec = NULL; - Value* ptrVal; - Value* arrayOffsetVal = NULL; - - // Test if a GetElemPtr instruction is being folded into this mem instrn. - // If so, it will be in the left child for Load and GetElemPtr, - // and in the right child for Store instructions. - // - InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store - ? vmInstrNode->rightChild() - : vmInstrNode->leftChild()); - - if (ptrChild->getOpLabel() == Instruction::GetElementPtr || - ptrChild->getOpLabel() == GetElemPtrIdx) - { - // There is a GetElemPtr instruction and there may be a chain of - // more than one. Use the pointer value of the last one in the chain. - // Fold the index vectors from the entire chain and from the mem - // instruction into one single index vector. - // Finally, we never fold for an array instruction so make that NULL. - - newIdxVec = new vector; - ptrVal = FoldGetElemChain((InstructionNode*) ptrChild, *newIdxVec); - - newIdxVec->insert(newIdxVec->end(), idxVec->begin(), idxVec->end()); - idxVec = newIdxVec; - - assert(! ((PointerType*)ptrVal->getType())->getValueType()->isArrayType() - && "GetElemPtr cannot be folded into array refs in selection"); - } - else - { - // There is no GetElemPtr instruction. - // Use the pointer value and the index vector from the Mem instruction. - // If it is an array reference, get the array offset value. - // - ptrVal = memInst->getPtrOperand(); - - const Type* opType = - ((const PointerType*) ptrVal->getType())->getValueType(); - if (opType->isArrayType()) - { - assert((memInst->getNumOperands() - == (unsigned) 1 + memInst->getFirstOffsetIdx()) - && "Array refs must be lowered before Instruction Selection"); - - arrayOffsetVal = memInst->getOperand(memInst->getFirstOffsetIdx()); - } - } - - SetMemOperands_Internal(minstr, vmInstrNode, ptrVal, arrayOffsetVal, - *idxVec, target); - - if (newIdxVec != NULL) - delete newIdxVec; -} - - -static void -SetMemOperands_Internal(MachineInstr* minstr, - const InstructionNode* vmInstrNode, - Value* ptrVal, - Value* arrayOffsetVal, - const vector& idxVec, - const TargetMachine& target) -{ - MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction(); - - // Initialize so we default to storing the offset in a register. - int64_t smallConstOffset; - Value* valueForRegOffset = NULL; - MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister; - - // Check if there is an index vector and if so, if it translates to - // a small enough constant to fit in the immediate-offset field. - // - if (idxVec.size() > 0) - { - bool isConstantOffset = false; - unsigned offset; - - const PointerType* ptrType = (PointerType*) ptrVal->getType(); - - if (ptrType->getValueType()->isStructType()) - { - // the offset is always constant for structs - isConstantOffset = true; - - // Compute the offset value using the index vector - offset = target.DataLayout.getIndexedOffset(ptrType, idxVec); - } - else - { - // It must be an array ref. Check if the offset is a constant, - // and that the indexing has been lowered to a single offset. - // - assert(ptrType->getValueType()->isArrayType()); - assert(arrayOffsetVal != NULL - && "Expect to be given Value* for array offsets"); - - if (ConstPoolVal *CPV = arrayOffsetVal->castConstant()) - { - isConstantOffset = true; // always constant for structs - assert(arrayOffsetVal->getType()->isIntegral()); - offset = (CPV->getType()->isSigned() - ? ((ConstPoolSInt*)CPV)->getValue() - : (int64_t) ((ConstPoolUInt*)CPV)->getValue()); - } - else - { - valueForRegOffset = arrayOffsetVal; - } - } - - if (isConstantOffset) - { - // create a virtual register for the constant - valueForRegOffset = ConstPoolSInt::get(Type::IntTy, offset); - } - } - else - { - offsetOpType = MachineOperand::MO_SignExtendedImmed; - smallConstOffset = 0; - } - - // Operand 0 is value for STORE, ptr for LOAD or GET_ELEMENT_PTR - // It is the left child in the instruction tree in all cases. - Value* leftVal = vmInstrNode->leftChild()->getValue(); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, leftVal); - - // Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR - // Operand 3 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR - // - unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1; - if (offsetOpType == MachineOperand::MO_VirtualRegister) - { - assert(valueForRegOffset != NULL); - minstr->SetMachineOperand(offsetOpNum, offsetOpType, valueForRegOffset); - } - else - minstr->SetMachineOperand(offsetOpNum, offsetOpType, smallConstOffset); - - if (memInst->getOpcode() == Instruction::Store) - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, ptrVal); - else - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - vmInstrNode->getValue()); -} - - -// Special handling for constant operands: -// -- if the constant is 0, use the hardwired 0 register, if any; -// -- if the constant is of float or double type but has an integer value, -// use int-to-float conversion instruction instead of generating a load; -// -- if the constant fits in the IMMEDIATE field, use that field; -// -- else insert instructions to put the constant into a register, either -// directly or by loading explicitly from the constant pool. -// -static unsigned -FixConstantOperands(const InstructionNode* vmInstrNode, - MachineInstr** mvec, - unsigned numInstr, - TargetMachine& target) -{ - static MachineInstr* loadConstVec[MAX_INSTR_PER_VMINSTR]; - - unsigned numNew = 0; - Instruction* vmInstr = vmInstrNode->getInstruction(); - - for (unsigned i=0; i < numInstr; i++) - { - MachineInstr* minstr = mvec[i]; - const MachineInstrDescriptor& instrDesc = - target.getInstrInfo().getDescriptor(minstr->getOpCode()); - - for (unsigned op=0; op < minstr->getNumOperands(); op++) - { - const MachineOperand& mop = minstr->getOperand(op); - - // skip the result position (for efficiency below) and any other - // positions already marked as not a virtual register - if (instrDesc.resultPos == (int) op || - mop.getOperandType() != MachineOperand::MO_VirtualRegister || - mop.getVRegValue() == NULL) - { - break; - } - - Value* opValue = mop.getVRegValue(); - - if (opValue->isConstant()) - { - unsigned int machineRegNum; - int64_t immedValue; - MachineOperand::MachineOperandType opType = - ChooseRegOrImmed(opValue, minstr->getOpCode(), target, - /*canUseImmed*/ (op == 1), - machineRegNum, immedValue); - - if (opType == MachineOperand::MO_MachineRegister) - minstr->SetMachineOperand(op, machineRegNum); - else if (opType == MachineOperand::MO_VirtualRegister) - { - // value is constant and must be loaded into a register - TmpInstruction* tmpReg; - MachineInstr* minstr2; - loadConstVec[numNew++] = MakeLoadConstInstr(vmInstr, opValue, - tmpReg, minstr2); - minstr->SetMachineOperand(op, opType, tmpReg); - if (minstr2 != NULL) - loadConstVec[numNew++] = minstr2; - } - else - minstr->SetMachineOperand(op, opType, immedValue); - } - } - } - - if (numNew > 0) - { - // Insert the new instructions *before* the old ones by moving - // the old ones over `numNew' positions (last-to-first, of course!). - // We do check *after* returning that we did not exceed the vector mvec. - for (int i=numInstr-1; i >= 0; i--) - mvec[i+numNew] = mvec[i]; - - for (unsigned i=0; i < numNew; i++) - mvec[i] = loadConstVec[i]; - } - - return (numInstr + numNew); -} - - -static inline MachineInstr* -MakeIntSetInstruction(int64_t C, bool isSigned, Value* dest) -{ - MachineInstr* minstr; - if (isSigned) - { - minstr = new MachineInstr(SETSW); - minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C); - } - else - { - minstr = new MachineInstr(SETUW); - minstr->SetMachineOperand(0, MachineOperand::MO_UnextendedImmed, C); - } - - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest); - - return minstr; -} - - -static MachineInstr* -MakeLoadConstInstr(Instruction* vmInstr, - Value* val, - TmpInstruction*& tmpReg, - MachineInstr*& getMinstr2) -{ - assert(val->isConstant()); - - MachineInstr* minstr; - - getMinstr2 = NULL; - - // Create a TmpInstruction to mark the hidden register used for the constant - tmpReg = new TmpInstruction(Instruction::UserOp1, val, NULL); - vmInstr->getMachineInstrVec().addTempValue(tmpReg); - - // Use a "set" instruction for known constants that can go in an integer reg. - // Use a "set" instruction followed by a int-to-float conversion for known - // constants that must go in a floating point reg but have an integer value. - // Use a "load" instruction for all other constants, in particular, - // floating point constants. - // - const Type* valType = val->getType(); - - if (valType->isIntegral() || - valType->isPointerType() || - valType == Type::BoolTy) - { - bool isValidConstant; - int64_t C = GetConstantValueAsSignedInt(val, isValidConstant); - assert(isValidConstant && "Unrecognized constant"); - - minstr = MakeIntSetInstruction(C, valType->isSigned(), tmpReg); - } - else - { - assert(valType == Type::FloatTy || valType == Type::DoubleTy); - double dval = ((ConstPoolFP*) val)->getValue(); - if (dval == (int64_t) dval) - { - // The constant actually has an integer value, so use a - // [set; int-to-float] sequence instead of a load instruction. - // - TmpInstruction* tmpReg2 = NULL; - if (dval != 0.0) - { // First, create an integer constant of the same value as dval - ConstPoolSInt* ival = ConstPoolSInt::get(Type::IntTy, - (int64_t) dval); - // Create another TmpInstruction for the hidden integer register - TmpInstruction* tmpReg2 = - new TmpInstruction(Instruction::UserOp1, ival, NULL); - vmInstr->getMachineInstrVec().addTempValue(tmpReg2); - - // Create the `SET' instruction - minstr = MakeIntSetInstruction((int64_t)dval, true, tmpReg2); - } - - // In which variable do we put the second instruction? - MachineInstr*& instr2 = (minstr)? getMinstr2 : minstr; - - // Create the int-to-float instruction - instr2 = new MachineInstr(valType == Type::FloatTy? FITOS : FITOD); - - if (dval == 0.0) - instr2->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0); - else - instr2->SetMachineOperand(0,MachineOperand::MO_VirtualRegister, - tmpReg2); - - instr2->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - tmpReg); - } - else - { - // Make a Load instruction, and make `val' both the ptr value *and* - // the result value, and set the offset field to 0. Final code - // generation will have to generate the base+offset for the constant. - // - int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0 - minstr = new MachineInstr(ChooseLoadInstruction(val->getType())); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,val); - minstr->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, - zeroOffset); - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - tmpReg); - } - } - - tmpReg->addMachineInstruction(minstr); - - assert(minstr); - return minstr; -} - -// -// Substitute operand `operandNum' of the instruction in node `treeNode' -// in place the use(s) of that instruction in node `parent'. -// -static void -ForwardOperand(InstructionNode* treeNode, - InstructionNode* parent, - int operandNum) -{ - Instruction* unusedOp = treeNode->getInstruction(); - Value* fwdOp = unusedOp->getOperand(operandNum); - Instruction* userInstr = parent->getInstruction(); - MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec(); - for (unsigned i=0, N=mvec.size(); i < N; i++) - { - MachineInstr* minstr = mvec[i]; - for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; i++) - { - const MachineOperand& mop = minstr->getOperand(i); - if (mop.getOperandType() == MachineOperand::MO_VirtualRegister && - mop.getVRegValue() == unusedOp) - { - minstr->SetMachineOperand(i, MachineOperand::MO_VirtualRegister, - fwdOp); - } - } - } -} - - -// This function is currently unused and incomplete but will be -// used if we have a linear layout of basic blocks in LLVM code. -// It decides which branch should fall-through, and whether an -// extra unconditional branch is needed (when neither falls through). -// -void -ChooseBranchPattern(Instruction* vmInstr, BranchPattern& brPattern) -{ - BranchInst* brInstr = (BranchInst*) vmInstr; - - brPattern.flipCondition = false; - brPattern.targetBB = brInstr->getSuccessor(0); - brPattern.extraBranch = NULL; - - assert(brInstr->getNumSuccessors() > 1 && - "Unnecessary analysis for unconditional branch"); - - assert(0 && "Fold branches in peephole optimization"); -} - - -//******************* Externally Visible Functions *************************/ - - -//------------------------------------------------------------------------ -// External Function: GetInstructionsByRule -// -// Purpose: -// Choose machine instructions for the SPARC according to the -// patterns chosen by the BURG-generated parser. -//------------------------------------------------------------------------ - -unsigned -GetInstructionsByRule(InstructionNode* subtreeRoot, - int ruleForNode, - short* nts, - TargetMachine &target, - MachineInstr** mvec) -{ - int numInstr = 1; // initialize for common case - bool checkCast = false; // initialize here to use fall-through - Value *leftVal, *rightVal; - const Type* opType; - int nextRule; - int forwardOperandNum = -1; - BranchPattern brPattern; - int64_t s0 = 0; // variables holding zero to avoid - uint64_t u0 = 0; // overloading ambiguities below - - mvec[0] = mvec[1] = mvec[2] = mvec[3] = NULL; // just for safety - - switch(ruleForNode) { - case 1: // stmt: Ret - case 2: // stmt: RetValue(reg) - // NOTE: Prepass of register allocation is responsible - // for moving return value to appropriate register. - // Mark the return-address register as a hidden virtual reg. - { - Instruction* returnReg = new TmpInstruction(Instruction::UserOp1, - subtreeRoot->getInstruction(), NULL); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(returnReg); - - mvec[0] = new MachineInstr(RETURN); - mvec[0]->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,returnReg); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0); - - returnReg->addMachineInstruction(mvec[0]); - - mvec[numInstr++] = new MachineInstr(NOP); // delay slot - break; - } - - case 3: // stmt: Store(reg,reg) - case 4: // stmt: Store(reg,ptrreg) - mvec[0] = new MachineInstr(ChooseStoreInstruction(subtreeRoot->leftChild()->getValue()->getType())); - SetOperandsForMemInstr(mvec[0], subtreeRoot, target); - break; - - case 5: // stmt: BrUncond - mvec[0] = new MachineInstr(BA); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, (Value*)NULL); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - break; - - case 6: // stmt: BrCond(boolconst) - // boolconst => boolean was computed with `%b = setCC type reg1 constant' - // If the constant is ZERO, we can use the branch-on-integer-register - // instructions and avoid the SUBcc instruction entirely. - // Otherwise this is just the same as case 5, so just fall through. - { - InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild(); - assert(constNode && constNode->getNodeType() ==InstrTreeNode::NTConstNode); - ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue(); - bool isValidConst; - - if (constVal->getType()->isIntegral() - && GetConstantValueAsSignedInt(constVal, isValidConst) == 0 - && isValidConst) - { - // That constant ia a zero after all... - // Use the left child of the setCC instruction as the first argument! - mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot)); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - - // false branch - mvec[numInstr++] = new MachineInstr(BA); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - (Value*) NULL); - mvec[numInstr-1]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - - break; - } - // ELSE FALL THROUGH - } - - case 7: // stmt: BrCond(bool) - // bool => boolean was computed with `%b = setcc type reg1 reg2' - // Need to check whether the type was a FP, signed int or unsigned int, - // and check the branching condition in order to choose the branch to use. - // - { - bool isFPBranch; - mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch)); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - - // false branch - mvec[numInstr++] = new MachineInstr(BA); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - (Value*) NULL); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - break; - } - - case 8: // stmt: BrCond(boolreg) - // bool => boolean is stored in an existing register. - // Just use the branch-on-integer-register instruction! - // - mvec[0] = new MachineInstr(BRNZ); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); // delay slot - - // false branch - mvec[numInstr++] = new MachineInstr(BA); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - (Value*) NULL); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - break; - - case 9: // stmt: Switch(reg) - assert(0 && "*** SWITCH instruction is not implemented yet."); - numInstr = 0; - break; - - case 10: // reg: VRegList(reg, reg) - assert(0 && "VRegList should never be the topmost non-chain rule"); - break; - - case 21: // reg: Not(reg): Implemented as reg = reg XOR-NOT 0 - mvec[0] = new MachineInstr(XNOR); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - break; - - case 22: // reg: ToBoolTy(reg): - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() || opType == Type::BoolTy); - numInstr = 0; - forwardOperandNum = 0; - break; - - case 23: // reg: ToUByteTy(reg) - case 25: // reg: ToUShortTy(reg) - case 27: // reg: ToUIntTy(reg) - case 29: // reg: ToULongTy(reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() || - opType->isPointerType() || - opType == Type::BoolTy && "Ignoring cast: illegal for other types"); - numInstr = 0; - forwardOperandNum = 0; - break; - - case 24: // reg: ToSByteTy(reg) - case 26: // reg: ToShortTy(reg) - case 28: // reg: ToIntTy(reg) - case 30: // reg: ToLongTy(reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - if (opType->isIntegral() || opType == Type::BoolTy) - { - numInstr = 0; - forwardOperandNum = 0; - } - else - { - mvec[0] =new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,opType)); - Set2OperandsFromInstr(mvec[0], subtreeRoot, target); - } - break; - - case 31: // reg: ToFloatTy(reg): - case 32: // reg: ToDoubleTy(reg): - - // If this instruction has a parent (a user) in the tree - // and the user is translated as an FsMULd instruction, - // then the cast is unnecessary. So check that first. - // In the future, we'll want to do the same for the FdMULq instruction, - // so do the check here instead of only for ToFloatTy(reg). - // - if (subtreeRoot->parent() != NULL && - ((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD) - { - numInstr = 0; - forwardOperandNum = 0; - } - else - { - opType = subtreeRoot->leftChild()->getValue()->getType(); - MachineOpCode opCode = ChooseConvertToFloatInstr(subtreeRoot, opType); - if (opCode == INVALID_OPCODE) // no conversion needed - { - numInstr = 0; - forwardOperandNum = 0; - } - else - { - mvec[0] = new MachineInstr(opCode); - Set2OperandsFromInstr(mvec[0], subtreeRoot, target); - } - } - break; - - case 19: // reg: ToArrayTy(reg): - case 20: // reg: ToPointerTy(reg): - numInstr = 0; - forwardOperandNum = 0; - break; - - case 233: // reg: Add(reg, Constant) - mvec[0] = CreateAddConstInstruction(subtreeRoot); - if (mvec[0] != NULL) - break; - // ELSE FALL THROUGH - - case 33: // reg: Add(reg, reg) - mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 234: // reg: Sub(reg, Constant) - mvec[0] = CreateSubConstInstruction(subtreeRoot); - if (mvec[0] != NULL) - break; - // ELSE FALL THROUGH - - case 34: // reg: Sub(reg, reg) - mvec[0] = new MachineInstr(ChooseSubInstruction(subtreeRoot)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 135: // reg: Mul(todouble, todouble) - checkCast = true; - // FALL THROUGH - - case 35: // reg: Mul(reg, reg) - mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 335: // reg: Mul(todouble, todoubleConst) - checkCast = true; - // FALL THROUGH - - case 235: // reg: Mul(reg, Constant) - mvec[0] = CreateMulConstInstruction(subtreeRoot, mvec[1]); - if (mvec[0] == NULL) - { - mvec[0]=new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - } - else - if (mvec[1] != NULL) - ++numInstr; - break; - - case 236: // reg: Div(reg, Constant) - mvec[0] = CreateDivConstInstruction(subtreeRoot, mvec[1]); - if (mvec[0] != NULL) - { - if (mvec[1] != NULL) - ++numInstr; - } - else - // ELSE FALL THROUGH - - case 36: // reg: Div(reg, reg) - mvec[0] = new MachineInstr(ChooseDivInstruction(subtreeRoot)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 37: // reg: Rem(reg, reg) - case 237: // reg: Rem(reg, Constant) - assert(0 && "REM instruction unimplemented for the SPARC."); - break; - - case 38: // reg: And(reg, reg) - case 238: // reg: And(reg, Constant) - mvec[0] = new MachineInstr(AND); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 138: // reg: And(reg, not) - mvec[0] = new MachineInstr(ANDN); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 39: // reg: Or(reg, reg) - case 239: // reg: Or(reg, Constant) - mvec[0] = new MachineInstr(ORN); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 139: // reg: Or(reg, not) - mvec[0] = new MachineInstr(ORN); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 40: // reg: Xor(reg, reg) - case 240: // reg: Xor(reg, Constant) - mvec[0] = new MachineInstr(XOR); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 140: // reg: Xor(reg, not) - mvec[0] = new MachineInstr(XNOR); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 41: // boolconst: SetCC(reg, Constant) - // Check if this is an integer comparison, and - // there is a parent, and the parent decided to use - // a branch-on-integer-register instead of branch-on-condition-code. - // If so, the SUBcc instruction is not required. - // (However, we must still check for constants to be loaded from - // the constant pool so that such a load can be associated with - // this instruction.) - // - // Otherwise this is just the same as case 42, so just fall through. - // - if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() && - subtreeRoot->parent() != NULL) - { - InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent(); - assert(parentNode->getNodeType() == InstrTreeNode::NTInstructionNode); - const vector& - minstrVec = parentNode->getInstruction()->getMachineInstrVec(); - MachineOpCode parentOpCode; - if (parentNode->getInstruction()->getOpcode() == Instruction::Br && - (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ && - parentOpCode <= BRGEZ) - { - numInstr = 0; // don't forward the operand! - break; - } - } - // ELSE FALL THROUGH - - case 42: // bool: SetCC(reg, reg): - { - // If result of the SetCC is only used for a branch, we can - // discard the result. otherwise, it must go into an integer register. - // Note that the user may or may not be in the same tree, so we have - // to follow SSA def-use edges here, not BURG tree edges. - // - Instruction* result = subtreeRoot->getInstruction(); - Value* firstUse = (Value*) * result->use_begin(); - bool discardResult = - (result->use_size() == 1 - && firstUse->isInstruction() - && ((Instruction*) firstUse)->getOpcode() == Instruction::Br); - - bool mustClearReg; - int valueToMove; - MachineOpCode movOpCode; - - if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() || - subtreeRoot->leftChild()->getValue()->getType()->isPointerType()) - { - // integer condition: destination should be %g0 or integer register - // if result must be saved but condition is not SetEQ then we need - // a separate instruction to compute the bool result, so discard - // result of SUBcc instruction anyway. - // - mvec[0] = new MachineInstr(SUBcc); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target, discardResult); - - // mark the 4th operand as being a CC register, and a "result" - mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister, - subtreeRoot->getValue(), /*def*/ true); - - if (!discardResult) - { // recompute bool if needed, using the integer condition codes - if (result->getOpcode() == Instruction::SetNE) - discardResult = true; - else - movOpCode = - ChooseMovpccAfterSub(subtreeRoot, mustClearReg, valueToMove); - } - } - else - { - // FP condition: dest of FCMP should be some FCCn register - mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot)); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - subtreeRoot->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->rightChild()->getValue()); - - if (!discardResult) - {// recompute bool using the FP condition codes - mustClearReg = true; - valueToMove = 1; - movOpCode = ChooseMovFpccInstruction(subtreeRoot); - } - } - - if (!discardResult) - { - if (mustClearReg) - {// Unconditionally set register to 0 - int n = numInstr++; - mvec[n] = new MachineInstr(SETHI); - mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,s0); - mvec[n]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - } - - // Now conditionally move `valueToMove' (0 or 1) into the register - int n = numInstr++; - mvec[n] = new MachineInstr(movOpCode); - mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - subtreeRoot->getValue()); - mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed, - valueToMove); - mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - } - break; - } - - case 43: // boolreg: VReg - case 44: // boolreg: Constant - numInstr = 0; - break; - - case 51: // reg: Load(reg) - case 52: // reg: Load(ptrreg) - case 53: // reg: LoadIdx(reg,reg) - case 54: // reg: LoadIdx(ptrreg,reg) - mvec[0] = new MachineInstr(ChooseLoadInstruction(subtreeRoot->getValue()->getType())); - SetOperandsForMemInstr(mvec[0], subtreeRoot, target); - break; - - case 55: // reg: GetElemPtr(reg) - case 56: // reg: GetElemPtrIdx(reg,reg) - if (subtreeRoot->parent() != NULL) - { - // Check if the parent was an array access. - // If so, we still need to generate this instruction. - MemAccessInst* memInst =(MemAccessInst*) subtreeRoot->getInstruction(); - const PointerType* ptrType = - (const PointerType*) memInst->getPtrOperand()->getType(); - if (! ptrType->getValueType()->isArrayType()) - {// we don't need a separate instr - numInstr = 0; // don't forward operand! - break; - } - } - // else in all other cases we need to a separate ADD instruction - mvec[0] = new MachineInstr(ADD); - SetOperandsForMemInstr(mvec[0], subtreeRoot, target); - break; - - case 57: // reg: Alloca: Implement as 2 instructions: - // sub %sp, tmp -> %sp - { // add %sp, 0 -> result - Instruction* instr = subtreeRoot->getInstruction(); - const PointerType* instrType = (const PointerType*) instr->getType(); - assert(instrType->isPointerType()); - int tsize = (int) target.findOptimalStorageSize(instrType->getValueType()); - assert(tsize != 0 && "Just to check when this can happen"); - // if (tsize == 0) - // { - // numInstr = 0; - // break; - // } - //else go on to create the instructions needed... - - // Create a temporary Value to hold the constant type-size - ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize); - - // Instruction 1: sub %sp, tsize -> %sp - // tsize is always constant, but it may have to be put into a - // register if it doesn't fit in the immediate field. - // - mvec[0] = new MachineInstr(SUB); - mvec[0]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize); - mvec[0]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - - // Instruction 2: add %sp, 0 -> result - numInstr++; - mvec[1] = new MachineInstr(ADD); - mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[1]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[1]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr); - break; - } - - case 58: // reg: Alloca(reg): Implement as 3 instructions: - // mul num, typeSz -> tmp - // sub %sp, tmp -> %sp - { // add %sp, 0 -> result - Instruction* instr = subtreeRoot->getInstruction(); - const PointerType* instrType = (const PointerType*) instr->getType(); - assert(instrType->isPointerType() && - instrType->getValueType()->isArrayType()); - const Type* eltType = - ((ArrayType*) instrType->getValueType())->getElementType(); - int tsize = (int) target.findOptimalStorageSize(eltType); - - assert(tsize != 0 && "Just to check when this can happen"); - // if (tsize == 0) - // { - // numInstr = 0; - // break; - // } - //else go on to create the instructions needed... - - // Create a temporary Value to hold the constant type-size - ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize); - - // Create a temporary value to hold `tmp' - Instruction* tmpInstr = new TmpInstruction(Instruction::UserOp1, - subtreeRoot->leftChild()->getValue(), - NULL /*could insert tsize here*/); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr); - - // Instruction 1: mul numElements, typeSize -> tmp - mvec[0] = new MachineInstr(MULX); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,tmpInstr); - - tmpInstr->addMachineInstruction(mvec[0]); - - // Instruction 2: sub %sp, tmp -> %sp - numInstr++; - mvec[1] = new MachineInstr(SUB); - mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,tmpInstr); - mvec[1]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - - // Instruction 3: add %sp, 0 -> result - numInstr++; - mvec[2] = new MachineInstr(ADD); - mvec[2]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[2]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[2]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr); - break; - } - - case 61: // reg: Call - // Generate a call-indirect (i.e., JMPL) for now to expose - // the potential need for registers. If an absolute address - // is available, replace this with a CALL instruction. - // Mark both the indirection register and the return-address - { // register as hidden virtual registers. - - Instruction* jmpAddrReg = new TmpInstruction(Instruction::UserOp1, - ((CallInst*) subtreeRoot->getInstruction())->getCalledMethod(), NULL); - Instruction* retAddrReg = new TmpInstruction(Instruction::UserOp1, - subtreeRoot->getValue(), NULL); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(jmpAddrReg); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(retAddrReg); - - mvec[0] = new MachineInstr(JMPL); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, jmpAddrReg); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, - (int64_t) 0); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, retAddrReg); - - // NOTE: jmpAddrReg will be loaded by a different instruction generated - // by the final code generator, so we just mark the CALL instruction - // as computing that value. - // The retAddrReg is actually computed by the CALL instruction. - // - jmpAddrReg->addMachineInstruction(mvec[0]); - retAddrReg->addMachineInstruction(mvec[0]); - - mvec[numInstr++] = new MachineInstr(NOP); // delay slot - break; - } - - case 62: // reg: Shl(reg, reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() || opType == Type::BoolTy); - mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 63: // reg: Shr(reg, reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() || opType == Type::BoolTy); - mvec[0] = new MachineInstr((opType->isSigned() - ? ((opType == Type::LongTy)? SRAX : SRA) - : ((opType == Type::LongTy)? SRLX : SRL))); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 64: // reg: Phi(reg,reg) - { // This instruction has variable #operands, so resultPos is 0. - Instruction* phi = subtreeRoot->getInstruction(); - mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands()); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - for (unsigned i=0, N=phi->getNumOperands(); i < N; i++) - mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister, - phi->getOperand(i)); - break; - } - case 71: // reg: VReg - case 72: // reg: Constant - numInstr = 0; // don't forward the value - break; - - case 111: // stmt: reg - case 112: // stmt: boolconst - case 113: // stmt: bool - case 121: - case 122: - case 123: - case 124: - case 125: - case 126: - case 127: - case 128: - case 129: - case 130: - case 131: - case 132: - case 153: - case 155: - // - // These are all chain rules, which have a single nonterminal on the RHS. - // Get the rule that matches the RHS non-terminal and use that instead. - // - assert(ThisIsAChainRule(ruleForNode)); - assert(nts[0] && ! nts[1] - && "A chain rule should have only one RHS non-terminal!"); - nextRule = burm_rule(subtreeRoot->state, nts[0]); - nts = burm_nts[nextRule]; - numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec); - break; - - default: - assert(0 && "Unrecognized BURG rule"); - numInstr = 0; - break; - } - - if (forwardOperandNum >= 0) - { // We did not generate a machine instruction but need to use operand. - // If user is in the same tree, replace Value in its machine operand. - // If not, insert a copy instruction which should get coalesced away - // by register allocation. - if (subtreeRoot->parent() != NULL) - ForwardOperand(subtreeRoot, (InstructionNode*) subtreeRoot->parent(), - forwardOperandNum); - else - { - int n = numInstr++; - mvec[n] = new MachineInstr(ADD); - mvec[n]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->getInstruction()->getOperand(forwardOperandNum)); - mvec[n]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->getInstruction()); - } - } - - if (! ThisIsAChainRule(ruleForNode)) - numInstr = FixConstantOperands(subtreeRoot, mvec, numInstr, target); - - return numInstr; -} - - diff --git a/lib/CodeGen/TargetMachine/Sparc/SparcInternals.h b/lib/CodeGen/TargetMachine/Sparc/SparcInternals.h deleted file mode 100644 index df290d63e72..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/SparcInternals.h +++ /dev/null @@ -1,1667 +0,0 @@ -//===-- SparcInternals.h - Header file for Sparc backend ---------*- C++ -*--=// -// -// This file defines stuff that is to be private to the Sparc backend, but is -// shared among different portions of the backend. -// -//===----------------------------------------------------------------------===// - -#ifndef SPARC_INTERNALS_H -#define SPARC_INTERNALS_H - -#include "llvm/CodeGen/Sparc.h" -#include "SparcRegInfo.h" - -#include -#include "llvm/Type.h" - -// OpCodeMask definitions for the Sparc V9 -// -const OpCodeMask Immed = 0x00002000; // immed or reg operand? -const OpCodeMask Annul = 0x20000000; // annul delay instr? -const OpCodeMask PredictTaken = 0x00080000; // predict branch taken? - - -enum SparcInstrSchedClass { - SPARC_NONE, /* Instructions with no scheduling restrictions */ - SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */ - SPARC_IEU0, /* Integer class IEU0 */ - SPARC_IEU1, /* Integer class IEU1 */ - SPARC_FPM, /* FP Multiply or Divide instructions */ - SPARC_FPA, /* All other FP instructions */ - SPARC_CTI, /* Control-transfer instructions */ - SPARC_LD, /* Load instructions */ - SPARC_ST, /* Store instructions */ - SPARC_SINGLE, /* Instructions that must issue by themselves */ - - SPARC_INV, /* This should stay at the end for the next value */ - SPARC_NUM_SCHED_CLASSES = SPARC_INV -}; - -// inline operator int (const SparcInstrSchedClass& si) { -// return (int) si; -// } -// -// inline operator SparcInstrSchedClass (int i) { -// return (SparcInstrSchedClass) si; -// } -// -// inline operator const SparcInstrSchedClass (int i) { -// return (const SparcInstrSchedClass) si; -// } - -//--------------------------------------------------------------------------- -// enum SparcMachineOpCode. -// const MachineInstrDescriptor SparcMachineInstrDesc[] -// -// Purpose: -// Description of UltraSparc machine instructions. -// -//--------------------------------------------------------------------------- - - -enum SparcMachineOpCode { - - NOP, - - // Synthetic SPARC assembly opcodes for setting a register to a constant - SETSW, - SETUW, - - // Set high-order bits of register and clear low-order bits - SETHI, - - // Add or add with carry. - // Immed bit specifies if second operand is immediate(1) or register(0) - ADD, - ADDcc, - ADDC, - ADDCcc, - - // Subtract or subtract with carry. - // Immed bit specifies if second operand is immediate(1) or register(0) - SUB, - SUBcc, - SUBC, - SUBCcc, - - // Integer multiply, signed divide, unsigned divide. - // Note that the deprecated 32-bit multiply and multiply-step are not used. - MULX, - SDIVX, - UDIVX, - - // Floating point add, subtract, compare - FADDS, - FADDD, - FADDQ, - FSUBS, - FSUBD, - FSUBQ, - FCMPS, - FCMPD, - FCMPQ, - // NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused! - - // Floating point multiply or divide. - FMULS, - FMULD, - FMULQ, - FSMULD, - FDMULQ, - FDIVS, - FDIVD, - FDIVQ, - FSQRTS, - FSQRTD, - FSQRTQ, - - // Logical operations - AND, - ANDcc, - ANDN, - ANDNcc, - OR, - ORcc, - ORN, - ORNcc, - XOR, - XORcc, - XNOR, - XNORcc, - - // Shift operations - SLL, - SRL, - SRA, - SLLX, - SRLX, - SRAX, - - // Floating point move, negate, and abs instructions - FMOVS, - FMOVD, -//FMOVQ, - FNEGS, - FNEGD, -//FNEGQ, - FABSS, - FABSD, -//FABSQ, - - // Convert from floating point to floating point formats - FSTOD, - FSTOQ, - FDTOS, - FDTOQ, - FQTOS, - FQTOD, - - // Convert from floating point to integer formats - FSTOX, - FDTOX, - FQTOX, - FSTOI, - FDTOI, - FQTOI, - - // Convert from integer to floating point formats - FXTOS, - FXTOD, - FXTOQ, - FITOS, - FITOD, - FITOQ, - - // Branch on integer comparison with zero. - // Annul bit specifies if intruction in delay slot is annulled(1) or not(0). - // PredictTaken bit hints if branch should be predicted taken(1) or not(0). - BRZ, - BRLEZ, - BRLZ, - BRNZ, - BRGZ, - BRGEZ, - - // Branch on integer condition code. - // Annul bit specifies if intruction in delay slot is annulled(1) or not(0). - // PredictTaken bit hints if branch should be predicted taken(1) or not(0). - BA, - BN, - BNE, - BE, - BG, - BLE, - BGE, - BL, - BGU, - BLEU, - BCC, - BCS, - BPOS, - BNEG, - BVC, - BVS, - - // Branch on floating point condition code. - // Annul bit specifies if intruction in delay slot is annulled(1) or not(0). - // PredictTaken bit hints if branch should be predicted taken(1) or not(0). - FBA, - FBN, - FBU, - FBG, - FBUG, - FBL, - FBUL, - FBLG, - FBNE, - FBE, - FBUE, - FBGE, - FBUGE, - FBLE, - FBULE, - FBO, - - // Conditional move on integer comparison with zero. - MOVRZ, - MOVRLEZ, - MOVRLZ, - MOVRNZ, - MOVRGZ, - MOVRGEZ, - - // Conditional move on integer condition code. - MOVA, - MOVN, - MOVNE, - MOVE, - MOVG, - MOVLE, - MOVGE, - MOVL, - MOVGU, - MOVLEU, - MOVCC, - MOVCS, - MOVPOS, - MOVNEG, - MOVVC, - MOVVS, - - // Conditional move on floating point condition code. - // Note that the enum name is not the same as the assembly mnemonic below - // because that would duplicate some entries with those above. - // Therefore, we use MOVF here instead of MOV. - MOVFA, - MOVFN, - MOVFU, - MOVFG, - MOVFUG, - MOVFL, - MOVFUL, - MOVFLG, - MOVFNE, - MOVFE, - MOVFUE, - MOVFGE, - MOVFUGE, - MOVFLE, - MOVFULE, - MOVFO, - - // Conditional move of floating point register on each of the above: - // i. on integer comparison with zero. - // ii. on integer condition code - // iii. on floating point condition code - // Note that the same set is repeated for S,D,Q register classes. - FMOVRSZ, - FMOVRSLEZ, - FMOVRSLZ, - FMOVRSNZ, - FMOVRSGZ, - FMOVRSGEZ, - - FMOVSA, - FMOVSN, - FMOVSNE, - FMOVSE, - FMOVSG, - FMOVSLE, - FMOVSGE, - FMOVSL, - FMOVSGU, - FMOVSLEU, - FMOVSCC, - FMOVSCS, - FMOVSPOS, - FMOVSNEG, - FMOVSVC, - FMOVSVS, - - FMOVSFA, - FMOVSFN, - FMOVSFU, - FMOVSFG, - FMOVSFUG, - FMOVSFL, - FMOVSFUL, - FMOVSFLG, - FMOVSFNE, - FMOVSFE, - FMOVSFUE, - FMOVSFGE, - FMOVSFUGE, - FMOVSFLE, - FMOVSFULE, - FMOVSFO, - - FMOVRDZ, - FMOVRDLEZ, - FMOVRDLZ, - FMOVRDNZ, - FMOVRDGZ, - FMOVRDGEZ, - - FMOVDA, - FMOVDN, - FMOVDNE, - FMOVDE, - FMOVDG, - FMOVDLE, - FMOVDGE, - FMOVDL, - FMOVDGU, - FMOVDLEU, - FMOVDCC, - FMOVDCS, - FMOVDPOS, - FMOVDNEG, - FMOVDVC, - FMOVDVS, - - FMOVDFA, - FMOVDFN, - FMOVDFU, - FMOVDFG, - FMOVDFUG, - FMOVDFL, - FMOVDFUL, - FMOVDFLG, - FMOVDFNE, - FMOVDFE, - FMOVDFUE, - FMOVDFGE, - FMOVDFUGE, - FMOVDFLE, - FMOVDFULE, - FMOVDFO, - - FMOVRQZ, - FMOVRQLEZ, - FMOVRQLZ, - FMOVRQNZ, - FMOVRQGZ, - FMOVRQGEZ, - - FMOVQA, - FMOVQN, - FMOVQNE, - FMOVQE, - FMOVQG, - FMOVQLE, - FMOVQGE, - FMOVQL, - FMOVQGU, - FMOVQLEU, - FMOVQCC, - FMOVQCS, - FMOVQPOS, - FMOVQNEG, - FMOVQVC, - FMOVQVS, - - FMOVQFA, - FMOVQFN, - FMOVQFU, - FMOVQFG, - FMOVQFUG, - FMOVQFL, - FMOVQFUL, - FMOVQFLG, - FMOVQFNE, - FMOVQFE, - FMOVQFUE, - FMOVQFGE, - FMOVQFUGE, - FMOVQFLE, - FMOVQFULE, - FMOVQFO, - - // Load integer instructions - LDSB, - LDSH, - LDSW, - LDUB, - LDUH, - LDUW, - LDX, - - // Load floating-point instructions - LD, - LDD, // use of this for integers is deprecated for Sparc V9 - LDQ, - - // Store integer instructions - STB, - STH, - STW, - STX, - - // Store floating-point instructions - ST, - STD, - - // Call, Return, and "Jump and link" - // Immed bit specifies if second operand is immediate(1) or register(0) - CALL, - JMPL, - RETURN, // last valid opcode - - // Synthetic phi operation for near-SSA form of machine code - PHI, - - // End-of-array marker - INVALID_OPCODE, - NUM_REAL_OPCODES = RETURN+1, // number of valid opcodes - NUM_TOTAL_OPCODES = INVALID_OPCODE -}; - -const MachineInstrDescriptor SparcMachineInstrDesc[] = { - - // Fields of each structure: - // opCodeString, - // numOperands, - // resultPosition (0-based; -1 if no result), - // maxImmedConst, - // immedIsSignExtended, - // numDelaySlots (in cycles) - // latency (in cycles) - // instr sched class (defined above) - // instr class flags (defined in TargretMachine.h) - - { "NOP", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG }, - - // Synthetic SPARC assembly opcodes for setting a register to a constant. - // Max immediate constant should be ignored for both these instructions. - { "SETSW", 2, 1, 0, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "SETUW", 2, 1, 0, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG }, - - // Set high-order bits of register and clear low-order bits - { "SETHI", 2, 1, (1 << 22) - 1, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG }, - - // Add or add with carry. - { "ADD", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "ADDcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG }, - { "ADDC", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "ADDCcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG }, - - // Sub tract or subtract with carry. - { "SUB", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "SUBcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG }, - { "SUBC", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "SUBCcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG }, - - // Integer multiply, signed divide, unsigned divide. - // Note that the deprecated 32-bit multiply and multiply-step are not used. - { "MULX", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "SDIVX", 3, 2, (1 << 12) - 1, true, 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - { "UDIVX", 3, 2, (1 << 12) - 1, true, 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG }, - - // Floating point add, subtract, compare. - // Note that destination of FCMP* instructions is operand 0, not operand 2. - { "FADDS", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FADDD", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FADDQ", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSUBS", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSUBD", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSUBQ", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FCMPS", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FCMPD", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FCMPQ", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - // NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused! - - // Floating point multiply or divide. - { "FMULS", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FMULD", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FMULQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSMULD", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FDMULQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FDIVS", 3, 2, 0, false, 0, 12, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FDIVD", 3, 2, 0, false, 0, 22, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FDIVQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSQRTS", 3, 2, 0, false, 0, 12, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSQRTD", 3, 2, 0, false, 0, 22, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSQRTQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG }, - - // Logical operations - { "AND", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG}, - { "ANDcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG}, - { "ANDN", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG}, - { "ANDNcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG}, - { "OR", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG}, - { "ORcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG}, - { "ORN", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG}, - { "ORNcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG}, - { "XOR", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG}, - { "XORcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG}, - { "XNOR", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG}, - { "XNORcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG}, - - // Shift operations - { "SLL", 3, 2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG}, - { "SRL", 3, 2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG}, - { "SRA", 3, 2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG }, - { "SLLX", 3, 2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG}, - { "SRLX", 3, 2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG}, - { "SRAX", 3, 2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG }, - - // Floating point move, negate, and abs instructions - { "FMOVS", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG }, - { "FMOVD", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG }, -//{ "FMOVQ", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG }, - { "FNEGS", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG }, - { "FNEGD", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG }, -//{ "FNEGQ", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG }, - { "FABSS", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG }, - { "FABSD", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG }, -//{ "FABSQ", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG }, - - // Convert from floating point to floating point formats - { "FSTOD", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FSTOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FDTOS", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FDTOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FQTOS", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - { "FQTOD", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG }, - - // Convert from floating point to integer formats. - // Note that this accesses both integer and floating point registers. - { "FSTOX", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FDTOX", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FQTOX", 2, 1, 0, false, 0, 2, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FSTOI", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FDTOI", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FQTOI", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - - // Convert from integer to floating point formats - // Note that this accesses both integer and floating point registers. - { "FXTOS", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FXTOD", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FXTOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FITOS", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FITOD", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - { "FITOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG }, - - // Branch on integer comparison with zero. - // Latency includes the delay slot. - { "BRZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG }, - { "BRLEZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG }, - { "BRLZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG }, - { "BRNZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG }, - { "BRGZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG }, - { "BRGEZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG }, - - // Branch on condition code. - // The first argument specifies the ICC register: %icc or %xcc - // Latency includes the delay slot. - { "BA", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BN", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BNE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BG", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BLE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BGE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BL", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BGU", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BLEU", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BCC", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BCS", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BPOS", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BNEG", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BVC", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "BVS", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - - // Branch on floating point condition code. - // Annul bit specifies if intruction in delay slot is annulled(1) or not(0). - // PredictTaken bit hints if branch should be predicted taken(1) or not(0). - // The first argument is the FCCn register (0 <= n <= 3). - // Latency includes the delay slot. - { "FBA", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBN", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBU", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBG", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBUG", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBL", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBUL", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBLG", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBNE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBUE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBGE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBUGE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBLE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBULE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - { "FBO", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG }, - - // Conditional move on integer comparison with zero. - { "MOVRZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG }, - { "MOVRLEZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG }, - { "MOVRLZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG }, - { "MOVRNZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG }, - { "MOVRGZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG }, - { "MOVRGEZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG }, - - // Conditional move on integer condition code. - // The first argument specifies the ICC register: %icc or %xcc - { "MOVA", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVN", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVNE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVLE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVGE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVL", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVGU", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVLEU", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVCC", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVCS", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVPOS", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVNEG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVVC", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVVS", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - - // Conditional move (of integer register) on floating point condition code. - // The first argument is the FCCn register (0 <= n <= 3). - // Note that the enum name above is not the same as the assembly mnemonic - // because some of the assembly mnemonics are the same as the move on - // integer CC (e.g., MOVG), and we cannot have the same enum entry twice. - { "MOVA", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVN", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVU", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVUG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVL", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVUL", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVLG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVNE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVUE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVGE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVUGE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVLE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVULE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - { "MOVO", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG }, - - // Conditional move of floating point register on each of the above: - // i. on integer comparison with zero. - // ii. on integer condition code - // iii. on floating point condition code - // Note that the same set is repeated for S,D,Q register classes. - { "FMOVRSZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRSLEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRSLZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRSNZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRSGZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRSGEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - - { "FMOVSA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSGU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSLEU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSCC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSCS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSPOS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSNEG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSVC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSVS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - - { "FMOVSA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSUG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSUL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSLG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSUE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSUGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSULE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVSO", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - - { "FMOVRDZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRDLEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRDLZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRDNZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRDGZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRDGEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - - { "FMOVDA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDGU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDLEU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDCC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDCS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDPOS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDNEG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDVC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDVS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - - { "FMOVDA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDUG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDUL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDLG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDUE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDUGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDULE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVDO", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - - { "FMOVRQZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRQLEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRQLZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRQNZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRQGZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - { "FMOVRQGEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG }, - - { "FMOVQA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQGU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQLEU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQCC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQCS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQPOS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQNEG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQVC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQVS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - - { "FMOVQA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQUG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQUL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQLG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQUE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQUGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQULE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - { "FMOVQO", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG }, - - // Load integer instructions - // Latency includes 1 cycle for address generation (Sparc IIi) - // Signed loads of less than 64 bits need an extra cycle for sign-extension. - // - // Not reflected here: After a 3-cycle loads, all subsequent consecutive - // loads also require 3 cycles to avoid contention for the load return - // stage. Latency returns to 2 cycles after the first cycle with no load. - { "LDSB", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - { "LDSH", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - { "LDSW", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - { "LDUB", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - { "LDUH", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - { "LDUW", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - { "LDX", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG }, - - // Load floating-point instructions - // Latency includes 1 cycle for address generation (Sparc IIi) - { "LD", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG }, - { "LDD", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG }, - { "LDQ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG }, - - // Store integer instructions - // Latency includes 1 cycle for address generation (Sparc IIi) - { "STB", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG }, - { "STH", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG }, - { "STW", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG }, - { "STX", 3, -1, (1 << 12) - 1, true, 0, 3, SPARC_ST, M_INT_FLAG | M_STORE_FLAG }, - - // Store floating-point instructions (Sparc IIi) - { "ST", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG}, - { "STD", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG}, - - // Call, Return and "Jump and link". - // Latency includes the delay slot. - { "CALL", 1, -1, (1 << 29) - 1, true, 1, 2, SPARC_CTI, M_BRANCH_FLAG | M_CALL_FLAG}, - { "JMPL", 3, -1, (1 << 12) - 1, true, 1, 2, SPARC_CTI, M_BRANCH_FLAG | M_CALL_FLAG}, - { "RETURN", 2, -1, 0, false, 1, 2, SPARC_CTI, M_BRANCH_FLAG | M_RET_FLAG }, - - // Synthetic phi operation for near-SSA form of machine code - // Number of operands is variable, indicated by -1. Result is the first op. - - { "PHI", -1, 0, 0, false, 0, 0, SPARC_INV, M_DUMMY_PHI_FLAG }, - -}; - - - -//--------------------------------------------------------------------------- -// class UltraSparcInstrInfo -// -// Purpose: -// Information about individual instructions. -// Most information is stored in the SparcMachineInstrDesc array above. -// Other information is computed on demand, and most such functions -// default to member functions in base class MachineInstrInfo. -//--------------------------------------------------------------------------- - -class UltraSparcInstrInfo : public MachineInstrInfo { -public: - /*ctor*/ UltraSparcInstrInfo(); - - virtual bool hasResultInterlock (MachineOpCode opCode) - { - // All UltraSPARC instructions have interlocks (note that delay slots - // are not considered here). - // However, instructions that use the result of an FCMP produce a - // 9-cycle stall if they are issued less than 3 cycles after the FCMP. - // Force the compiler to insert a software interlock (i.e., gap of - // 2 other groups, including NOPs if necessary). - return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ); - } - -}; - -//--------------------------------------------------------------------------- -// class UltraSparcInstrInfo -// -// Purpose: -// This class provides info about sparc register classes. -//--------------------------------------------------------------------------- - -class LiveRange; - -class UltraSparcRegInfo : public MachineRegInfo -{ - - private: - enum RegClassIDs { IntRegClassID, FloatRegClassID, FloatCCREgClassID }; - - // reverse pointer to get info about the ultra sparc machine - const UltraSparc *const UltraSparcInfo; - - // Int arguments can be passed in 6 int regs - %o0 to %o5 (cannot be changed) - unsigned const NumOfIntArgRegs; - - // Float arguments can be passed in this many regs - can be canged if needed - // %f0 - %f5 are used (can hold 6 floats or 3 doubles) - unsigned const NumOfFloatArgRegs; - - void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const; - - - public: - - UltraSparcRegInfo(const UltraSparc *USI ) : UltraSparcInfo(USI), - NumOfIntArgRegs(6), - NumOfFloatArgRegs(6) - { - - MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) ); - MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) ); - - assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 && - "6 Float regs are used for float arg passing"); - - } - - inline const UltraSparc & getUltraSparcInfo() const { - return *UltraSparcInfo; - } - - inline unsigned getRegClassIDOfValue (const Value *const Val) const { - Type::PrimitiveID ty = (Val->getType())->getPrimitiveID(); - - if( ty && ty <= Type::LongTyID || (ty == Type::PointerTyID) ) - return IntRegClassID; // sparc int reg (ty=0: void) - else if( ty <= Type::DoubleTyID) - return FloatRegClassID; // sparc float reg class - else { - cout << "TypeID: " << ty << endl; - assert(0 && "Cannot resolve register class for type"); - - } - } - - void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const; - - static void printReg(const LiveRange *const LR) ; - - void colorCallArgs(vector & CallInstrList, - LiveRangeInfo& LRI, - AddedInstrMapType& AddedInstrMap ) const; - - // this method provides a unique number for each register - inline int getUnifiedRegNum(int RegClassID, int reg) const { - - if( RegClassID == IntRegClassID && reg < 32 ) - return reg; - else if ( RegClassID == FloatRegClassID && reg < 64) - return reg + 32; // we have 32 int regs - else if( RegClassID == FloatCCREgClassID && reg < 4) - return reg + 32 + 64; // 32 int, 64 float - else - assert(0 && "Invalid register class or reg number"); - - } - - // given the unified register number, this gives the name - inline const string getUnifiedRegName(int reg) const { - - if( reg < 32 ) - return SparcIntRegOrder::getRegName(reg); - else if ( reg < (64 + 32) ) - return SparcFloatRegOrder::getRegName( reg - 32); - else if( reg < (64+32+4) ) - assert( 0 && "no float condition reg class yet"); - // return reg + 32 + 64; - else - assert(0 && "Invalid register number"); - } - - -}; - - - - - - - -/*--------------------------------------------------------------------------- -Scheduling guidelines for SPARC IIi: - -I-Cache alignment rules (pg 326) --- Align a branch target instruction so that it's entire group is within - the same cache line (may be 1-4 instructions). -** Don't let a branch that is predicted taken be the last instruction - on an I-cache line: delay slot will need an entire line to be fetched --- Make a FP instruction or a branch be the 4th instruction in a group. - For branches, there are tradeoffs in reordering to make this happen - (see pg. 327). -** Don't put a branch in a group that crosses a 32-byte boundary! - An artificial branch is inserted after every 32 bytes, and having - another branch will force the group to be broken into 2 groups. - -iTLB rules: --- Don't let a loop span two memory pages, if possible - -Branch prediction performance: --- Don't make the branch in a delay slot the target of a branch --- Try not to have 2 predicted branches within a group of 4 instructions - (because each such group has a single branch target field). --- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid - the wrong prediction bits being used in some cases). - -D-Cache timing constraints: --- Signed int loads of less than 64 bits have 3 cycle latency, not 2 --- All other loads that hit in D-Cache have 2 cycle latency --- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit --- Mis-aligned loads or stores cause a trap. In particular, replace - mis-aligned FP double precision l/s with 2 single-precision l/s. --- Simulations of integer codes show increase in avg. group size of - 33% when code (including esp. non-faulting loads) is moved across - one branch, and 50% across 2 branches. - -E-Cache timing constraints: --- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering) - -Store buffer timing constraints: --- Stores can be executed in same cycle as instruction producing the value --- Stores are buffered and have lower priority for E-cache until - highwater mark is reached in the store buffer (5 stores) - -Pipeline constraints: --- Shifts can only use IEU0. --- CC setting instructions can only use IEU1. --- Several other instructions must only use IEU1: - EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP. --- Two instructions cannot store to the same register file in a single cycle - (single write port per file). - -Issue and grouping constraints: --- FP and branch instructions must use slot 4. --- Shift instructions cannot be grouped with other IEU0-specific instructions. --- CC setting instructions cannot be grouped with other IEU1-specific instrs. --- Several instructions must be issued in a single-instruction group: - MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others --- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs. --- --- - -Branch delay slot scheduling rules: --- A CTI couple (two back-to-back CTI instructions in the dynamic stream) - has a 9-instruction penalty: the entire pipeline is flushed when the - second instruction reaches stage 9 (W-Writeback). --- Avoid putting multicycle instructions, and instructions that may cause - load misses, in the delay slot of an annulling branch. --- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the - delay slot of an annulling branch. - - *--------------------------------------------------------------------------- */ - -//--------------------------------------------------------------------------- -// List of CPUResources for UltraSPARC IIi. -//--------------------------------------------------------------------------- - -const CPUResource AllIssueSlots( "All Instr Slots", 4); -const CPUResource IntIssueSlots( "Int Instr Slots", 3); -const CPUResource First3IssueSlots("Instr Slots 0-3", 3); -const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1); -const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1); -const CPUResource FPAIssueSlots( "Int Instr Slot 1", 1); -const CPUResource FPMIssueSlots( "Int Instr Slot 1", 1); - -// IEUN instructions can use either Alu and should use IAluN. -// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0. -// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1. -const CPUResource IAluN("Int ALU 1or2", 2); -const CPUResource IAlu0("Int ALU 1", 1); -const CPUResource IAlu1("Int ALU 2", 1); - -const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1); -const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1); -const CPUResource LdReturn("Load Return Unit", 1); - -const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1); -const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1); -const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1); - -const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1); -const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1); -const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1); - -const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK -const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK -const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX); // CHECK -const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK - -const CPUResource CTIDelayCycle( "CTI delay cycle", 1); -const CPUResource FCMPDelayCycle("FCMP delay cycle", 1); - - -//--------------------------------------------------------------------------- -// const InstrClassRUsage SparcRUsageDesc[] -// -// Purpose: -// Resource usage information for instruction in each scheduling class. -// The InstrRUsage Objects for individual classes are specified first. -// Note that fetch and decode are decoupled from the execution pipelines -// via an instr buffer, so they are not included in the cycles below. -//--------------------------------------------------------------------------- - -const InstrClassRUsage NoneClassRUsage = { - SPARC_NONE, - /*totCycles*/ 7, - - /* maxIssueNum */ 4, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 4, - /* feasibleSlots[] */ { 0, 1, 2, 3 }, - - /*numEntries*/ 0, - /* V[] */ { - /*Cycle G */ - /*Cycle E */ - /*Cycle C */ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ - } -}; - -const InstrClassRUsage IEUNClassRUsage = { - SPARC_IEUN, - /*totCycles*/ 7, - - /* maxIssueNum */ 3, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 3, - /* feasibleSlots[] */ { 0, 1, 2 }, - - /*numEntries*/ 4, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { IntIssueSlots.rid, 0, 1 }, - /*Cycle E */ { IAluN.rid, 1, 1 }, - /*Cycle C */ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ { IRegWritePorts.rid, 6, 1 } - } -}; - -const InstrClassRUsage IEU0ClassRUsage = { - SPARC_IEU0, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 3, - /* feasibleSlots[] */ { 0, 1, 2 }, - - /*numEntries*/ 5, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { IntIssueSlots.rid, 0, 1 }, - /*Cycle E */ { IAluN.rid, 1, 1 }, - { IAlu0.rid, 1, 1 }, - /*Cycle C */ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ { IRegWritePorts.rid, 6, 1 } - } -}; - -const InstrClassRUsage IEU1ClassRUsage = { - SPARC_IEU1, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 3, - /* feasibleSlots[] */ { 0, 1, 2 }, - - /*numEntries*/ 5, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { IntIssueSlots.rid, 0, 1 }, - /*Cycle E */ { IAluN.rid, 1, 1 }, - { IAlu1.rid, 1, 1 }, - /*Cycle C */ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ { IRegWritePorts.rid, 6, 1 } - } -}; - -const InstrClassRUsage FPMClassRUsage = { - SPARC_FPM, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 4, - /* feasibleSlots[] */ { 0, 1, 2, 3 }, - - /*numEntries*/ 7, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { FPMIssueSlots.rid, 0, 1 }, - /*Cycle E */ { FPRegReadPorts.rid, 1, 1 }, - /*Cycle C */ { FPMAluC1.rid, 2, 1 }, - /*Cycle N1*/ { FPMAluC2.rid, 3, 1 }, - /*Cycle N1*/ { FPMAluC3.rid, 4, 1 }, - /*Cycle N1*/ - /*Cycle W */ { FPRegWritePorts.rid, 6, 1 } - } -}; - -const InstrClassRUsage FPAClassRUsage = { - SPARC_FPA, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 4, - /* feasibleSlots[] */ { 0, 1, 2, 3 }, - - /*numEntries*/ 7, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { FPAIssueSlots.rid, 0, 1 }, - /*Cycle E */ { FPRegReadPorts.rid, 1, 1 }, - /*Cycle C */ { FPAAluC1.rid, 2, 1 }, - /*Cycle N1*/ { FPAAluC2.rid, 3, 1 }, - /*Cycle N1*/ { FPAAluC3.rid, 4, 1 }, - /*Cycle N1*/ - /*Cycle W */ { FPRegWritePorts.rid, 6, 1 } - } -}; - -const InstrClassRUsage LDClassRUsage = { - SPARC_LD, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 3, - /* feasibleSlots[] */ { 0, 1, 2, }, - - /*numEntries*/ 6, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { First3IssueSlots.rid, 0, 1 }, - { LSIssueSlots.rid, 0, 1 }, - /*Cycle E */ { LSAluC1.rid, 1, 1 }, - /*Cycle C */ { LSAluC2.rid, 2, 1 }, - { LdReturn.rid, 2, 1 }, - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ { IRegWritePorts.rid, 6, 1 } - } -}; - -const InstrClassRUsage STClassRUsage = { - SPARC_ST, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 3, - /* feasibleSlots[] */ { 0, 1, 2 }, - - /*numEntries*/ 4, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { First3IssueSlots.rid, 0, 1 }, - { LSIssueSlots.rid, 0, 1 }, - /*Cycle E */ { LSAluC1.rid, 1, 1 }, - /*Cycle C */ { LSAluC2.rid, 2, 1 } - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ - } -}; - -const InstrClassRUsage CTIClassRUsage = { - SPARC_CTI, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ false, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 4, - /* feasibleSlots[] */ { 0, 1, 2, 3 }, - - /*numEntries*/ 4, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { CTIIssueSlots.rid, 0, 1 }, - /*Cycle E */ { IAlu0.rid, 1, 1 }, - /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 } - /*Cycle C */ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ - } -}; - -const InstrClassRUsage SingleClassRUsage = { - SPARC_SINGLE, - /*totCycles*/ 7, - - /* maxIssueNum */ 1, - /* isSingleIssue */ true, - /* breaksGroup */ false, - /* numBubbles */ 0, - - /*numSlots*/ 1, - /* feasibleSlots[] */ { 0 }, - - /*numEntries*/ 5, - /* V[] */ { - /*Cycle G */ { AllIssueSlots.rid, 0, 1 }, - { AllIssueSlots.rid, 0, 1 }, - { AllIssueSlots.rid, 0, 1 }, - { AllIssueSlots.rid, 0, 1 }, - /*Cycle E */ { IAlu0.rid, 1, 1 } - /*Cycle C */ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle N1*/ - /*Cycle W */ - } -}; - - -const InstrClassRUsage SparcRUsageDesc[] = { - NoneClassRUsage, - IEUNClassRUsage, - IEU0ClassRUsage, - IEU1ClassRUsage, - FPMClassRUsage, - FPAClassRUsage, - CTIClassRUsage, - LDClassRUsage, - STClassRUsage, - SingleClassRUsage -}; - - -//--------------------------------------------------------------------------- -// const InstrIssueDelta SparcInstrIssueDeltas[] -// -// Purpose: -// Changes to issue restrictions information in InstrClassRUsage for -// instructions that differ from other instructions in their class. -//--------------------------------------------------------------------------- - -const InstrIssueDelta SparcInstrIssueDeltas[] = { - - // opCode, isSingleIssue, breaksGroup, numBubbles - - // Special cases for single-issue only - // Other single issue cases are below. -//{ LDDA, true, true, 0 }, -//{ STDA, true, true, 0 }, -//{ LDDF, true, true, 0 }, -//{ LDDFA, true, true, 0 }, - { ADDC, true, true, 0 }, - { ADDCcc, true, true, 0 }, - { SUBC, true, true, 0 }, - { SUBCcc, true, true, 0 }, -//{ SAVE, true, true, 0 }, -//{ RESTORE, true, true, 0 }, -//{ LDSTUB, true, true, 0 }, -//{ SWAP, true, true, 0 }, -//{ SWAPA, true, true, 0 }, -//{ CAS, true, true, 0 }, -//{ CASA, true, true, 0 }, -//{ CASX, true, true, 0 }, -//{ CASXA, true, true, 0 }, -//{ LDFSR, true, true, 0 }, -//{ LDFSRA, true, true, 0 }, -//{ LDXFSR, true, true, 0 }, -//{ LDXFSRA, true, true, 0 }, -//{ STFSR, true, true, 0 }, -//{ STFSRA, true, true, 0 }, -//{ STXFSR, true, true, 0 }, -//{ STXFSRA, true, true, 0 }, -//{ SAVED, true, true, 0 }, -//{ RESTORED, true, true, 0 }, -//{ FLUSH, true, true, 9 }, -//{ FLUSHW, true, true, 9 }, -//{ ALIGNADDR, true, true, 0 }, - { RETURN, true, true, 0 }, -//{ DONE, true, true, 0 }, -//{ RETRY, true, true, 0 }, -//{ WR, true, true, 0 }, -//{ WRPR, true, true, 4 }, -//{ RD, true, true, 0 }, -//{ RDPR, true, true, 0 }, -//{ TCC, true, true, 0 }, -//{ SHUTDOWN, true, true, 0 }, - - // Special cases for breaking group *before* - // CURRENTLY NOT SUPPORTED! - { CALL, false, false, 0 }, - { JMPL, false, false, 0 }, - - // Special cases for breaking the group *after* - { MULX, true, true, (4+34)/2 }, - { FDIVS, false, true, 0 }, - { FDIVD, false, true, 0 }, - { FDIVQ, false, true, 0 }, - { FSQRTS, false, true, 0 }, - { FSQRTD, false, true, 0 }, - { FSQRTQ, false, true, 0 }, -//{ FCMP{LE,GT,NE,EQ}, false, true, 0 }, - - // Instructions that introduce bubbles -//{ MULScc, true, true, 2 }, -//{ SMULcc, true, true, (4+18)/2 }, -//{ UMULcc, true, true, (4+19)/2 }, - { SDIVX, true, true, 68 }, - { UDIVX, true, true, 68 }, -//{ SDIVcc, true, true, 36 }, -//{ UDIVcc, true, true, 37 }, -//{ WR, false, false, 4 }, -//{ WRPR, false, false, 4 }, -}; - - -//--------------------------------------------------------------------------- -// const InstrRUsageDelta SparcInstrUsageDeltas[] -// -// Purpose: -// Changes to resource usage information in InstrClassRUsage for -// instructions that differ from other instructions in their class. -//--------------------------------------------------------------------------- - -const InstrRUsageDelta SparcInstrUsageDeltas[] = { - - // MachineOpCode, Resource, Start cycle, Num cycles - - // - // JMPL counts as a load/store instruction for issue! - // - { JMPL, LSIssueSlots.rid, 0, 1 }, - - // - // Many instructions cannot issue for the next 2 cycles after an FCMP - // We model that with a fake resource FCMPDelayCycle. - // - { FCMPS, FCMPDelayCycle.rid, 1, 3 }, - { FCMPD, FCMPDelayCycle.rid, 1, 3 }, - { FCMPQ, FCMPDelayCycle.rid, 1, 3 }, - - { MULX, FCMPDelayCycle.rid, 1, 1 }, - { SDIVX, FCMPDelayCycle.rid, 1, 1 }, - { UDIVX, FCMPDelayCycle.rid, 1, 1 }, -//{ SMULcc, FCMPDelayCycle.rid, 1, 1 }, -//{ UMULcc, FCMPDelayCycle.rid, 1, 1 }, -//{ SDIVcc, FCMPDelayCycle.rid, 1, 1 }, -//{ UDIVcc, FCMPDelayCycle.rid, 1, 1 }, - { STD, FCMPDelayCycle.rid, 1, 1 }, - { FMOVRSZ, FCMPDelayCycle.rid, 1, 1 }, - { FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 }, - { FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 }, - { FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 }, - { FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 }, - { FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 }, - - // - // Some instructions are stalled in the GROUP stage if a CTI is in - // the E or C stage - // - { LDD, CTIDelayCycle.rid, 1, 1 }, -//{ LDDA, CTIDelayCycle.rid, 1, 1 }, -//{ LDDSTUB, CTIDelayCycle.rid, 1, 1 }, -//{ LDDSTUBA, CTIDelayCycle.rid, 1, 1 }, -//{ SWAP, CTIDelayCycle.rid, 1, 1 }, -//{ SWAPA, CTIDelayCycle.rid, 1, 1 }, -//{ CAS, CTIDelayCycle.rid, 1, 1 }, -//{ CASA, CTIDelayCycle.rid, 1, 1 }, -//{ CASX, CTIDelayCycle.rid, 1, 1 }, -//{ CASXA, CTIDelayCycle.rid, 1, 1 }, - - // - // Signed int loads of less than dword size return data in cycle N1 (not C) - // and put all loads in consecutive cycles into delayed load return mode. - // - { LDSB, LdReturn.rid, 2, -1 }, - { LDSB, LdReturn.rid, 3, 1 }, - - { LDSH, LdReturn.rid, 2, -1 }, - { LDSH, LdReturn.rid, 3, 1 }, - - { LDSW, LdReturn.rid, 2, -1 }, - { LDSW, LdReturn.rid, 3, 1 }, - - -#undef EXPLICIT_BUBBLES_NEEDED -#ifdef EXPLICIT_BUBBLES_NEEDED - // - // MULScc inserts one bubble. - // This means it breaks the current group (captured in UltraSparcSchedInfo) - // *and occupies all issue slots for the next cycle - // -//{ MULScc, AllIssueSlots.rid, 2, 2-1 }, -//{ MULScc, AllIssueSlots.rid, 2, 2-1 }, -//{ MULScc, AllIssueSlots.rid, 2, 2-1 }, -//{ MULScc, AllIssueSlots.rid, 2, 2-1 }, - - // - // SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1. - // We just model this with a simple average. - // -//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 }, -//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 }, -//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 }, -//{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 }, - - // SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1. -//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 }, -//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 }, -//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 }, -//{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 }, - - // - // MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1. - // - { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 }, - { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 }, - { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 }, - { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 }, - - // - // SDIVcc inserts 36 bubbles. - // -//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 }, -//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 }, -//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 }, -//{ SDIVcc, AllIssueSlots.rid, 2, 36-1 }, - - // UDIVcc inserts 37 bubbles. -//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 }, -//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 }, -//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 }, -//{ UDIVcc, AllIssueSlots.rid, 2, 37-1 }, - - // - // SDIVX inserts 68 bubbles. - // - { SDIVX, AllIssueSlots.rid, 2, 68-1 }, - { SDIVX, AllIssueSlots.rid, 2, 68-1 }, - { SDIVX, AllIssueSlots.rid, 2, 68-1 }, - { SDIVX, AllIssueSlots.rid, 2, 68-1 }, - - // - // UDIVX inserts 68 bubbles. - // - { UDIVX, AllIssueSlots.rid, 2, 68-1 }, - { UDIVX, AllIssueSlots.rid, 2, 68-1 }, - { UDIVX, AllIssueSlots.rid, 2, 68-1 }, - { UDIVX, AllIssueSlots.rid, 2, 68-1 }, - - // - // WR inserts 4 bubbles. - // -//{ WR, AllIssueSlots.rid, 2, 68-1 }, -//{ WR, AllIssueSlots.rid, 2, 68-1 }, -//{ WR, AllIssueSlots.rid, 2, 68-1 }, -//{ WR, AllIssueSlots.rid, 2, 68-1 }, - - // - // WRPR inserts 4 bubbles. - // -//{ WRPR, AllIssueSlots.rid, 2, 68-1 }, -//{ WRPR, AllIssueSlots.rid, 2, 68-1 }, -//{ WRPR, AllIssueSlots.rid, 2, 68-1 }, -//{ WRPR, AllIssueSlots.rid, 2, 68-1 }, - - // - // DONE inserts 9 bubbles. - // -//{ DONE, AllIssueSlots.rid, 2, 9-1 }, -//{ DONE, AllIssueSlots.rid, 2, 9-1 }, -//{ DONE, AllIssueSlots.rid, 2, 9-1 }, -//{ DONE, AllIssueSlots.rid, 2, 9-1 }, - - // - // RETRY inserts 9 bubbles. - // -//{ RETRY, AllIssueSlots.rid, 2, 9-1 }, -//{ RETRY, AllIssueSlots.rid, 2, 9-1 }, -//{ RETRY, AllIssueSlots.rid, 2, 9-1 }, -//{ RETRY, AllIssueSlots.rid, 2, 9-1 }, - -#endif EXPLICIT_BUBBLES_NEEDED -}; - - - -// Additional delays to be captured in code: -// 1. RDPR from several state registers (page 349) -// 2. RD from *any* register (page 349) -// 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349) -// 4. Integer store can be in same group as instr producing value to store. -// 5. BICC and BPICC can be in the same group as instr producing CC (pg 350) -// 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351). -// 7. The second instr. of a CTI group inserts 9 bubbles (pg 351) -// 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that -// follow an annulling branch cannot be issued in the same group or in -// the 3 groups following the branch. -// 9. A predicted annulled load does not stall dependent instructions. -// Other annulled delay slot instructions *do* stall dependents, so -// nothing special needs to be done for them during scheduling. -//10. Do not put a load use that may be annulled in the same group as the -// branch. The group will stall until the load returns. -//11. Single-prec. FP loads lock 2 registers, for dependency checking. -// -// -// Additional delays we cannot or will not capture: -// 1. If DCTI is last word of cache line, it is delayed until next line can be -// fetched. Also, other DCTI alignment-related delays (pg 352) -// 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache. -// Also, several other store-load and load-store conflicts (pg 358) -// 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358) -// 4. There can be at most 8 outstanding buffered store instructions -// (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH) - - - -//--------------------------------------------------------------------------- -// class UltraSparcSchedInfo -// -// Purpose: -// Interface to instruction scheduling information for UltraSPARC. -// The parameter values above are based on UltraSPARC IIi. -//--------------------------------------------------------------------------- - - -class UltraSparcSchedInfo: public MachineSchedInfo { -public: - /*ctor*/ UltraSparcSchedInfo (const MachineInstrInfo* mii); - /*dtor*/ virtual ~UltraSparcSchedInfo () {} -protected: - virtual void initializeResources (); -}; - -#endif diff --git a/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.cpp b/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.cpp deleted file mode 100644 index c3a52209fe1..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.cpp +++ /dev/null @@ -1,301 +0,0 @@ -#include "SparcInternals.h" -#include "llvm/CodeGen/IGNode.h" - - -//----------------------------------------------------------------------------- -// Int Register Class -//----------------------------------------------------------------------------- - -void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const -{ - - /* Algorithm: - Record the color of all neighbors. - - If there is no call interf, try to allocate volatile, then non volatile - If there is call interf, try to allocate non-volatile. If that fails - try to allocate a volatile and insert save across calls - If both above fail, spill. - - */ - - unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors - - for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh - IGNode *NeighIGNode = Node->getAdjIGNode(n); - if( NeighIGNode->hasColor() ) { // if neigh has a color - IsColorUsedArr[ NeighIGNode->getColor() ] = true; // record that color - } - } - - - - unsigned SearchStart; // start pos of color in pref-order - bool ColorFound= false; // have we found a color yet? - - //if this Node is between calls - if( Node->getNumOfCallInterferences() == 0) { - - // start with volatiles (we can allocate volatiles safely) - SearchStart = SparcIntRegOrder::StartOfAllRegs; - } - else { - // start with non volatiles (no non-volatiles) - SearchStart = SparcIntRegOrder::StartOfNonVolatileRegs; - } - - unsigned c=0; // color - - // find first unused color - for( c=SearchStart; c < SparcIntRegOrder::NumOfAvailRegs; c++) { - if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; } - } - - if( ColorFound) - Node->setColor(c); // first color found in preffered order - - // if color is not found because of call interference - // try even finding a volatile color and insert save across calls - else if( Node->getNumOfCallInterferences() ) - { - // start from 0 - try to find even a volatile this time - SearchStart = SparcIntRegOrder::StartOfAllRegs; - - // find first unused volatile color - for(c=SearchStart; c < SparcIntRegOrder::StartOfNonVolatileRegs; c++) { - if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; } - } - - if( ColorFound) { - Node->setColor(c); - // since LR span across calls, must save across calls - Node->markForSaveAcrossCalls(); - } - - } - - // If we couldn't find a color regardless of call interference - i.e., we - // don't have either a volatile or non-volatile color left - if( !ColorFound ) - Node->markForSpill(); // no color found - must spill - - - if( DEBUG_RA) - UltraSparcRegInfo::printReg( Node->getParentLR() ); - -} - - - - - - -//----------------------------------------------------------------------------- -// Float Register Class -//----------------------------------------------------------------------------- - -// find the first available color in the range [Start,End] depending on the -// type of the Node (i.e., float/double) - -int SparcFloatRegClass::findFloatColor(const IGNode *const Node, unsigned Start, - unsigned End, - bool IsColorUsedArr[] ) const -{ - - bool ColorFound = false; - unsigned c; - - if( Node->getTypeID() == Type::DoubleTyID ) { - - // find first unused color for a double - for( c=Start; c < End ;c+= 2){ - if( ! IsColorUsedArr[ c ] && ! IsColorUsedArr[ c+1 ]) - { ColorFound=true; break; } - } - - } else { - - // find first unused color for a single - for( c=Start; c < End; c++) { - if( ! IsColorUsedArr[ c ] ) { ColorFound=true; break; } - } - } - - if( ColorFound ) return c; - else return -1; -} - - - - - -void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const -{ - - /* Algorithm: - - If the LR is a double try to allocate f32 - f63 - If the above fails or LR is single precision - If the LR does not interfere with a call - start allocating from f0 - Else start allocating from f6 - If a color is still not found because LR interferes with a call - Search in f0 - f6. If found mark for spill across calls. - If a color is still not fond, mark for spilling - */ - - - unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors - - for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh - IGNode *NeighIGNode = Node->getAdjIGNode(n); - if( NeighIGNode->hasColor() ) { // if neigh has a color - IsColorUsedArr[ NeighIGNode->getColor() ] = true; // record that color - if( NeighIGNode->getTypeID() == Type::DoubleTyID ) - IsColorUsedArr[ (NeighIGNode->getColor()) + 1 ] = true; - } - } - - int ColorFound = -1; // have we found a color yet? - unsigned NumOfCallInterf = Node->getNumOfCallInterferences(); - - // if value is a double - search the double only reigon (f32 - f63) - if( Node->getTypeID() == Type::DoubleTyID ) - ColorFound = findFloatColor( Node, 32, 64, IsColorUsedArr ); - - - if( ColorFound >= 0 ) { - Node->setColor(ColorFound); - if( DEBUG_RA) UltraSparcRegInfo::printReg( Node->getParentLR() ); - return; - } - - else { // the above fails or LR is single precision - - unsigned SearchStart; // start pos of color in pref-order - - //if this Node is between calls (i.e., no call interferences ) - if( ! NumOfCallInterf ) { - // start with volatiles (we can allocate volatiles safely) - SearchStart = SparcFloatRegOrder::StartOfAllRegs; - } - else { - // start with non volatiles (no non-volatiles) - SearchStart = SparcFloatRegOrder::StartOfNonVolatileRegs; - } - - ColorFound = findFloatColor( Node, SearchStart, 32, IsColorUsedArr ); - - } - - if( ColorFound >= 0 ) { - Node->setColor(ColorFound); - if( DEBUG_RA) UltraSparcRegInfo::printReg( Node->getParentLR() ); - return; - } - - else if( NumOfCallInterf ) { - - // We are here because there is a call interference and no non-volatile - // color could be found. - // Now try to allocate even a volatile color - - ColorFound = findFloatColor( Node, SparcFloatRegOrder::StartOfAllRegs, - SparcFloatRegOrder::StartOfNonVolatileRegs, - IsColorUsedArr); - } - - if( ColorFound >= 0 ) { - Node->setColor(ColorFound); // first color found in preffered order - Node->markForSaveAcrossCalls(); - if( DEBUG_RA) UltraSparcRegInfo::printReg( Node->getParentLR() ); - return; - } - - else { - Node->markForSpill(); // no color found - must spill - if( DEBUG_RA) UltraSparcRegInfo::printReg( Node->getParentLR() ); - } - - -} - - - - - - -#if 0 - -//----------------------------------------------------------------------------- -// Float Register Class -//----------------------------------------------------------------------------- - -void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const -{ - - /* Algorithm: - Record the color of all neighbors. - - Single precision can use f0 - f31 - Double precision can use f0 - f63 - - if LR is a double, try to allocate f32 - f63. - if the above attempt fails, or Value is single presion, try to allcoate - f0 - f31. - - */ - - unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors - - for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh - IGNode *NeighIGNode = Node->getAdjIGNode(n); - if( NeighIGNode->hasColor() ) { // if neigh has a color - IsColorUsedArr[ NeighIGNode->getColor() ] = true; // record that color - if( NeighIGNode->getTypeID() == Type::DoubleTyID ) - IsColorUsedArr[ (NeighIGNode->getColor()) + 1 ] = true; - } - } - - - unsigned SearchStart; // start pos of color in pref-order - bool ColorFound= false; // have we found a color yet? - unsigned c; - - - if( Node->getTypeID() == Type::DoubleTyID ) { // if value is a double - - // search the double only reigon (f32 - f63) - for( c=32; c < 64; c+= 2) { - if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; } - } - - // search f0 - f31 region - if( ! ColorFound ) { // if color not found - for( c=0; c < 32; c+= 2) { - if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; } - } - } - - } - - else { // value is Single - - for( c=0; c < 32; c++) { - if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; } - } - } - - - if( ColorFound) - Node->setColor(c); // first color found in preferred order - else - Node->markForSpill(); // no color found - must spill - - - if( DEBUG_RA) - UltraSparcRegInfo::printReg( Node->getParentLR() ); - -} - -#endif diff --git a/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.h b/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.h deleted file mode 100644 index 41a6d00a081..00000000000 --- a/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.h +++ /dev/null @@ -1,167 +0,0 @@ -/* Title: SparcRegClassInfo.h -*- C++ -*- - Author: Ruchira Sasanka - Date: Aug 20, 01 - Purpose: Contains the description of integer register class of Sparc -*/ - - -#ifndef SPARC_INT_REG_CLASS_H -#define SPARC_INT_REG_CLASS_H - -#include "llvm/CodeGen/TargetMachine.h" - -//----------------------------------------------------------------------------- -// Integer Register Class -//----------------------------------------------------------------------------- - - -// Int register names in same order as enum in class SparcIntRegOrder - -static string const IntRegNames[] = - { "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", - "g0", "i6", "i7", "o6" }; - - - -class SparcIntRegOrder{ - - public: - - enum RegsInPrefOrder // colors possible for a LR (in preferred order) - { - // --- following colors are volatile across function calls - // %g0 can't be used for coloring - always 0 - - g1, g2, g3, g4, g5, g6, g7, //%g1-%g7 - o0, o1, o2, o3, o4, o5, o7, // %o0-%o5, - - // %o6 is sp, - // all %0's can get modified by a call - - // --- following colors are NON-volatile across function calls - - l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7 - i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved - - // %i6 is the fp - so not allocated - // %i7 is the ret address - can be used if saved - - // max # of colors reg coloring can allocate (NumOfAvailRegs) - - // --- following colors are not available for allocation within this phase - // --- but can appear for pre-colored ranges - - g0, i6, i7, o6 - - - - }; - - // max # of colors reg coloring can allocate - static unsigned int const NumOfAvailRegs = g0; - - static unsigned int const StartOfNonVolatileRegs = l0; - static unsigned int const StartOfAllRegs = g1; - static unsigned int const NumOfAllRegs = o6 + 1; - - - static const string getRegName(const unsigned reg) { - assert( reg < NumOfAllRegs ); - return IntRegNames[reg]; - } - -}; - - - -class SparcIntRegClass : public MachineRegClassInfo -{ - public: - - SparcIntRegClass(unsigned ID) - : MachineRegClassInfo(0, - SparcIntRegOrder::NumOfAvailRegs, - SparcIntRegOrder::NumOfAllRegs) - { } - - void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const; - -}; - -//----------------------------------------------------------------------------- -// Float Register Class -//----------------------------------------------------------------------------- - -static string const FloatRegNames[] = - { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", - "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", - "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", - "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", - "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", - "f60", "f61", "f62", "f63" - }; - - -class SparcFloatRegOrder{ - - public: - - enum RegsInPrefOrder { - - f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, - f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, - f20, f21, f22, f23, f24, f25, f26, f27, f28, f29, - f30, f31, f32, f33, f34, f35, f36, f37, f38, f39, - f40, f41, f42, f43, f44, f45, f46, f47, f48, f49, - f50, f51, f52, f53, f54, f55, f56, f57, f58, f59, - f60, f61, f62, f63 - - }; - - // there are 64 regs alltogether but only 32 regs can be allocated at - // a time. - - static unsigned int const NumOfAvailRegs = 32; - static unsigned int const NumOfAllRegs = 64; - - static unsigned int const StartOfNonVolatileRegs = f6; - static unsigned int const StartOfAllRegs = f0; - - - static const string getRegName(const unsigned reg) { - assert( reg < NumOfAllRegs ); - return FloatRegNames[reg]; - } - - - -}; - - -class SparcFloatRegClass : public MachineRegClassInfo -{ - private: - - int findFloatColor(const IGNode *const Node, unsigned Start, - unsigned End, bool IsColorUsedArr[] ) const; - - public: - - SparcFloatRegClass(unsigned ID) - : MachineRegClassInfo(1, - SparcFloatRegOrder::NumOfAvailRegs, - SparcFloatRegOrder::NumOfAllRegs) - { } - - void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const; - -}; - - - -#endif