From: Duraid Madina <duraid@octopus.com.au>
Date: Wed, 8 Mar 2006 06:18:46 +0000 (+0000)
Subject: doo de doo
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1ffd41ab9927be0fb2d2ddaf1fed6c85f00140d9;p=oota-llvm.git

doo de doo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26614 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index a4e6cba1a2e..b41b67f79e4 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -25,6 +25,16 @@ def SDT_IA64RetFlag : SDTypeProfile<0, 0, []>;
 def retflag         : SDNode<"IA64ISD::RET_FLAG", SDT_IA64RetFlag,
 	                   [SDNPHasChain, SDNPOptInFlag]>;
 
+//===---------
+// Instruction types
+
+class isA { bit A=1; } // I or M unit
+class isM { bit M=1; } // M unit
+class isI { bit I=1; } // I unit
+class isB { bit B=1; } // B unit
+class isF { bit F=1; } // F unit
+class isLX { bit LX=1; } // I/B
+
 //===---------
 
 def u2imm : Operand<i8>;
@@ -105,48 +115,48 @@ def imm64  : PatLeaf<(i64 imm)>;
 
 def ADD  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
            "add $dst = $src1, $src2",
-	   [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
+	   [(set GR:$dst, (add GR:$src1, GR:$src2))]>, isA;
 
 def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
            "add $dst = $src1, $src2, 1",
-	   [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
+	   [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>, isA;
 
 def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
            "adds $dst = $imm, $src1",
-	   [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
+	   [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>, isA;
  
 def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
            "movl $dst = $imm",
-	   [(set GR:$dst, imm64:$imm)]>;
+	   [(set GR:$dst, imm64:$imm)]>, isLX;
 
 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
            "addl $dst = $imm, $src1",
-	   []>;
+	   []>, isA;
 
 // hmm 
 def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
            "addl $dst = $imm, $src1",
-	   []>;
+	   []>, isA;
  
 def SUB  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2",
-	   [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
+	   [(set GR:$dst, (sub GR:$src1, GR:$src2))]>, isA;
 
 def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2, 1",
-	   [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
+	   [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>, isA;
 
 let isTwoAddress = 1 in {
 def TPCADDIMM22 : AForm<0x03, 0x0b,
   (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
-    "($qp) add $dst = $imm, $dst">;
+    "($qp) add $dst = $imm, $dst">, isA;
 def TPCADDS : AForm_DAG<0x03, 0x0b,
   (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp),
     "($qp) adds $dst = $imm, $dst",
-    []>;
+    []>, isA;
 def TPCMPIMM8NE : AForm<0x03, 0x0b,
   (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
-    "($qp) cmp.ne $dst , p0 = $imm, $src2">;
+    "($qp) cmp.ne $dst , p0 = $imm, $src2">, isA;
 }
 
 // zero extend a bool (predicate reg) into an integer reg
@@ -155,66 +165,66 @@ def ZXTb : Pat<(zext PR:$src),
 
 // normal sign/zero-extends
 def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src",
-           [(set GR:$dst, (sext_inreg GR:$src, i8))]>;
+           [(set GR:$dst, (sext_inreg GR:$src, i8))]>, isI;
 def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src",
-           [(set GR:$dst, (and GR:$src, 255))]>;
+           [(set GR:$dst, (and GR:$src, 255))]>, isI;
 def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src",
-           [(set GR:$dst, (sext_inreg GR:$src, i16))]>;
+           [(set GR:$dst, (sext_inreg GR:$src, i16))]>, isI;
 def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src",
-           [(set GR:$dst, (and GR:$src, 65535))]>;
+           [(set GR:$dst, (and GR:$src, 65535))]>, isI;
 def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src",
-           [(set GR:$dst, (sext_inreg GR:$src, i32))]>;
+           [(set GR:$dst, (sext_inreg GR:$src, i32))]>, isI;
 def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src",
-           [(set GR:$dst, (and GR:$src, is32ones))]>;
+           [(set GR:$dst, (and GR:$src, is32ones))]>, isI;
 
 // fixme: shrs vs shru?
 def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix1.l $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
-	                     (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>;
+	                     (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>, isI;
 
 def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix2.l $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
-	                     (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>;
+	                     (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>, isI;
 
 def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix4.l $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
-	                     (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>;
+	                     (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>, isI;
 
 def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix1.r $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
-	                     (and GR:$src2, isMIX1Rable)))]>;
+	                     (and GR:$src2, isMIX1Rable)))]>, isI;
 
 def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix2.r $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
-	                     (and GR:$src2, isMIX2Rable)))]>;
+	                     (and GR:$src2, isMIX2Rable)))]>, isI;
 
 def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix4.r $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
-	                     (and GR:$src2, isMIX4Rable)))]>;
+	                     (and GR:$src2, isMIX4Rable)))]>, isI;
 
 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
   "getf.sig $dst = $src",
-  []>;
+  []>, isM;
 
 def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src),
   "setf.sig $dst = $src",
-  []>;
+  []>, isM;
 
 def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "xma.l $dst = $src1, $src2, $src3",
-  []>;
+  []>, isF;
 def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "xma.h $dst = $src1, $src2, $src3",
-  []>;
+  []>, isF;
 def XMAHUD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "xma.hu $dst = $src1, $src2, $src3",
-  []>;
+  []>, isF;
 
 // pseudocode for integer multiplication 
 def : Pat<(mul GR:$src1, GR:$src2),
@@ -232,94 +242,94 @@ def : Pat<(mulhu GR:$src1, GR:$src2),
 
 def AND   : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "and $dst = $src1, $src2",
-	  [(set GR:$dst, (and GR:$src1, GR:$src2))]>;
+	  [(set GR:$dst, (and GR:$src1, GR:$src2))]>, isA;
 def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "andcm $dst = $src1, $src2",
-	  [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>;
+	  [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>, isA;
 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
 def OR    : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "or $dst = $src1, $src2",
-	  [(set GR:$dst, (or GR:$src1, GR:$src2))]>;
+	  [(set GR:$dst, (or GR:$src1, GR:$src2))]>, isA;
 
 def pOR   : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
-          "($qp) or $dst = $src1, $src2">;
+          "($qp) or $dst = $src1, $src2">, isA;
 
 // the following are all a bit unfortunate: we throw away the complement
 // of the compare!
 def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.eq $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>, isA;
 def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.gt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>, isA;
 def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.ge $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setge GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setge GR:$src1, GR:$src2))]>, isA;
 def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.lt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>, isA;
 def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.le $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setle GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setle GR:$src1, GR:$src2))]>, isA;
 def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.ne $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setne GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setne GR:$src1, GR:$src2))]>, isA;
 def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.ltu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setult GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setult GR:$src1, GR:$src2))]>, isA;
 def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.gtu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>, isA;
 def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.leu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setule GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setule GR:$src1, GR:$src2))]>, isA;
 def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
           "cmp.geu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
+	  [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>, isA;
 
 // and we do the whole thing again for FP compares!
 def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.eq $dst, p0 = $src1, $src2",
-          [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>;
+          [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>, isF;
 def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.gt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>, isF;
 def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.ge $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setge FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setge FP:$src1, FP:$src2))]>, isF;
 def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.lt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>, isF;
 def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.le $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setle FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setle FP:$src1, FP:$src2))]>, isF;
 def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.neq $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setne FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF;
 def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.ltu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setult FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF;
 def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.gtu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF;
 def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.leu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setule FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF;
 def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
           "fcmp.geu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>;
+	  [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF;
 
 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp),
-    "($qp) cmp.eq.unc $dst, p0 = r0, r0">;
+    "($qp) cmp.eq.unc $dst, p0 = r0, r0">, isA;
 
 def : Pat<(trunc GR:$src),  // truncate i64 to i1
           (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true
 	  
 let isTwoAddress=1 in {
   def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
-    "($qp) cmp.eq $dst, p0 = r0, r0">;
+    "($qp) cmp.eq $dst, p0 = r0, r0">, isA;
   def TPCMPNER0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
-    "($qp) cmp.ne $dst, p0 = r0, r0">;
+    "($qp) cmp.ne $dst, p0 = r0, r0">, isA;
 }
 
 /* our pseudocode for OR on predicates is:
@@ -384,46 +394,46 @@ def bXOR  : Pat<(xor PR:$src1, PR:$src2),
 
 def XOR   : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "xor $dst = $src1, $src2",
-	  [(set GR:$dst, (xor GR:$src1, GR:$src2))]>;
+	  [(set GR:$dst, (xor GR:$src1, GR:$src2))]>, isA;
 
 def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
           "shladd $dst = $src1, $imm, $src2",
-          [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>;
+          [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>, isA;
 
 def SHL   : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "shl $dst = $src1, $src2",
-	  [(set GR:$dst, (shl GR:$src1, GR:$src2))]>;
+	  [(set GR:$dst, (shl GR:$src1, GR:$src2))]>, isI;
 
 def SHRU  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "shr.u $dst = $src1, $src2",
-	  [(set GR:$dst, (srl GR:$src1, GR:$src2))]>;
+	  [(set GR:$dst, (srl GR:$src1, GR:$src2))]>, isI;
 
 def SHRS  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "shr $dst = $src1, $src2",
-	  [(set GR:$dst, (sra GR:$src1, GR:$src2))]>;
+	  [(set GR:$dst, (sra GR:$src1, GR:$src2))]>, isI;
 
-def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src">;
+def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src">, isA;
 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "mov $dst = $src">; // XXX: there _is_ no fmov
+  "mov $dst = $src">, isF; // XXX: there _is_ no fmov
 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
-  "($qp) mov $dst = $src">;
+  "($qp) mov $dst = $src">, isA;
 
 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
-  "mov $dst = pr">;
+  "mov $dst = pr">, isI;
 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
-  "mov pr = $src">;
+  "mov pr = $src">, isI;
 
 let isTwoAddress = 1 in {
   def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
-    "($qp) mov $dst = $src">;
+    "($qp) mov $dst = $src">, isA;
 }
 
 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
-  "($qp) mov $dst = $src">;
+  "($qp) mov $dst = $src">, isF;
 
 let isTwoAddress = 1 in {
   def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
-    "($qp) mov $dst = $src">;
+    "($qp) mov $dst = $src">, isF;
 }
 
 def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
@@ -464,206 +474,206 @@ def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">;
 
 def ALLOC : AForm<0x03, 0x0b,
   (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
-    "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating">;
+    "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating">, isM;
 
 let isTwoAddress = 1 in {
   def TCMPNE : AForm<0x03, 0x0b,
   (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
-    "cmp.ne $dst, p0 = $src3, $src4">;
+    "cmp.ne $dst, p0 = $src3, $src4">, isA;
   
   def TPCMPEQOR : AForm<0x03, 0x0b,
   (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
-    "($qp) cmp.eq.or $dst, p0 = $src3, $src4">;
+    "($qp) cmp.eq.or $dst, p0 = $src3, $src4">, isA;
   
   def TPCMPNE : AForm<0x03, 0x0b,
   (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
-    "($qp) cmp.ne $dst, p0 = $src3, $src4">;
+    "($qp) cmp.ne $dst, p0 = $src3, $src4">, isA;
   
   def TPCMPEQ : AForm<0x03, 0x0b,
   (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
-    "($qp) cmp.eq $dst, p0 = $src3, $src4">;
+    "($qp) cmp.eq $dst, p0 = $src3, $src4">, isA;
 }
 
 def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
-  "mov $dst = $imm">;
+  "mov $dst = $imm">, isA;
 def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
-  "mov $dst = $imm">;
+  "mov $dst = $imm">, isA;
 def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
-  "movl $dst = $imm">;
+  "movl $dst = $imm">, isLX;
 
 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), 
-  "shl $dst = $src1, $imm">;
+  "shl $dst = $src1, $imm">, isI;
 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
-  "shr.u $dst = $src1, $imm">;
+  "shr.u $dst = $src1, $imm">, isI;
 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
-  "shr $dst = $src1, $imm">;
+  "shr $dst = $src1, $imm">, isI;
 
 def EXTRU : AForm<0x03, 0x0b,
   (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
-  "extr.u $dst = $src1, $imm1, $imm2">;
+  "extr.u $dst = $src1, $imm1, $imm2">, isI;
 
 def DEPZ : AForm<0x03, 0x0b,
   (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
-  "dep.z $dst = $src1, $imm1, $imm2">;
+  "dep.z $dst = $src1, $imm1, $imm2">, isI;
 
 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
-  "($qp) cmp.eq.or $dst, p0 = $src1, $src2">;
+  "($qp) cmp.eq.or $dst, p0 = $src1, $src2">, isA;
 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
-  "($qp) cmp.eq.unc $dst, p0 = $src1, $src2">;
+  "($qp) cmp.eq.unc $dst, p0 = $src1, $src2">, isA;
 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
-  "($qp) cmp.ne $dst, p0 = $src1, $src2">;
+  "($qp) cmp.ne $dst, p0 = $src1, $src2">, isA;
 
 // two destinations! 
 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
-  "cmp.eq $dst1, dst2 = $src1, $src2">;
+  "cmp.eq $dst1, dst2 = $src1, $src2">, isA;
 
 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
-  "adds $dst = $imm, $src1">;
+  "adds $dst = $imm, $src1">, isA;
 
 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
-  "add $dst = $imm, $src1">;
+  "add $dst = $imm, $src1">, isA;
 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
-  "($qp) add $dst = $imm, $src1">;
+  "($qp) add $dst = $imm, $src1">, isA;
 
 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
-  "sub $dst = $imm, $src2">;
+  "sub $dst = $imm, $src2">, isA;
 
 let isStore = 1, noResults = 1 in {
   def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
-    "st1 [$dstPtr] = $value">;
+    "st1 [$dstPtr] = $value">, isM;
   def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
-    "st2 [$dstPtr] = $value">;
+    "st2 [$dstPtr] = $value">, isM;
   def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
-    "st4 [$dstPtr] = $value">;
+    "st4 [$dstPtr] = $value">, isM;
   def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
-    "st8 [$dstPtr] = $value">;
+    "st8 [$dstPtr] = $value">, isM;
   def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
-    "stfs [$dstPtr] = $value">;
+    "stfs [$dstPtr] = $value">, isM;
   def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
-    "stfd [$dstPtr] = $value">;
+    "stfd [$dstPtr] = $value">, isM;
   def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
-    "stf.spill [$dstPtr] = $value">;
+    "stf.spill [$dstPtr] = $value">, isM;
 }
 
 let isLoad = 1 in {
   def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
-    "ld1 $dst = [$srcPtr]">;
+    "ld1 $dst = [$srcPtr]">, isM;
   def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
-    "ld2 $dst = [$srcPtr]">;
+    "ld2 $dst = [$srcPtr]">, isM;
   def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
-    "ld4 $dst = [$srcPtr]">;
+    "ld4 $dst = [$srcPtr]">, isM;
   def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
-    "ld8 $dst = [$srcPtr]">;
+    "ld8 $dst = [$srcPtr]">, isM;
   def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
-    "ldfs $dst = [$srcPtr]">;
+    "ldfs $dst = [$srcPtr]">, isM;
   def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
-    "ldfd $dst = [$srcPtr]">;
+    "ldfd $dst = [$srcPtr]">, isM;
   def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
-    "ldf.fill $dst = [$srcPtr]">;
+    "ldf.fill $dst = [$srcPtr]">, isM;
 }
 
 def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),
   "popcnt $dst = $src",
-  [(set GR:$dst, (ctpop GR:$src))]>;
+  [(set GR:$dst, (ctpop GR:$src))]>, isI;
 
 // some FP stuff:  // TODO: single-precision stuff?
 def FADD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
   "fadd $dst = $src1, $src2",
-  [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>;
+  [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>, isF;
 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
-  "fadd.s $dst = $src1, $src2">;
+  "fadd.s $dst = $src1, $src2">, isF;
 def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
   "fsub $dst = $src1, $src2",
-  [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>;
+  [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>, isF;
 def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
   "fmpy $dst = $src1, $src2",
-  [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>;
+  [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>, isF;
 def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "fma $dst = $src1, $src2, $src3",
-  [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>;
+  [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF;
 def FMS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "fms $dst = $src1, $src2, $src3",
-  [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>;
+  [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF;
 def FNMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "fnma $dst = $src1, $src2, $src3",
-  [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>;
+  [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>, isF;
 def FABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
   "fabs $dst = $src",
-  [(set FP:$dst, (fabs FP:$src))]>;
+  [(set FP:$dst, (fabs FP:$src))]>, isF;
 def FNEG : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
   "fneg $dst = $src",
-  [(set FP:$dst, (fneg FP:$src))]>;
+  [(set FP:$dst, (fneg FP:$src))]>, isF;
 def FNEGABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
   "fnegabs $dst = $src",
-  [(set FP:$dst, (fneg (fabs FP:$src)))]>;
+  [(set FP:$dst, (fneg (fabs FP:$src)))]>, isF;
 
 let isTwoAddress=1 in {
 def TCFMAS1 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fma.s1 $dst = $src1, $src2, $src3">;
+    "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF;
 def TCFMADS0 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fma.d.s0 $dst = $src1, $src2, $src3">;
+    "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF;
 }
 
 def CFMAS1 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fma.s1 $dst = $src1, $src2, $src3">;
+    "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF;
 def CFNMAS1 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fnma.s1 $dst = $src1, $src2, $src3">;
+    "($qp) fnma.s1 $dst = $src1, $src2, $src3">, isF;
 
 def CFMADS1 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fma.d.s1 $dst = $src1, $src2, $src3">;
+    "($qp) fma.d.s1 $dst = $src1, $src2, $src3">, isF;
 def CFMADS0 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fma.d.s0 $dst = $src1, $src2, $src3">;
+    "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF;
 def CFNMADS1 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
-    "($qp) fnma.d.s1 $dst = $src1, $src2, $src3">;
+    "($qp) fnma.d.s1 $dst = $src1, $src2, $src3">, isF;
 
 def FRCPAS0 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
-  "frcpa.s0 $dstFR, $dstPR = $src1, $src2">;
+  "frcpa.s0 $dstFR, $dstPR = $src1, $src2">, isF;
 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
-  "frcpa.s1 $dstFR, $dstPR = $src1, $src2">;
+  "frcpa.s1 $dstFR, $dstPR = $src1, $src2">, isF;
 
 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
-  "xma.l $dst = $src1, $src2, $src3">;
+  "xma.l $dst = $src1, $src2, $src3">, isF;
 
 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.xf $dst = $src">;
+  "fcvt.xf $dst = $src">, isF;
 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.xuf $dst = $src">;
+  "fcvt.xuf $dst = $src">, isF;
 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.xuf.s1 $dst = $src">;
+  "fcvt.xuf.s1 $dst = $src">, isF;
 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.fx $dst = $src">;
+  "fcvt.fx $dst = $src">, isF;
 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.fxu $dst = $src">;
+  "fcvt.fxu $dst = $src">, isF;
 
 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.fx.trunc $dst = $src">;
+  "fcvt.fx.trunc $dst = $src">, isF;
 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.fxu.trunc $dst = $src">;
+  "fcvt.fxu.trunc $dst = $src">, isF;
 
 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.fx.trunc.s1 $dst = $src">;
+  "fcvt.fx.trunc.s1 $dst = $src">, isF;
 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fcvt.fxu.trunc.s1 $dst = $src">;
+  "fcvt.fxu.trunc.s1 $dst = $src">, isF;
 
 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "fnorm.d $dst = $src">;
+  "fnorm.d $dst = $src">, isF;
 
 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
-  "getf.d $dst = $src">;
+  "getf.d $dst = $src">, isM;
 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
-  "setf.d $dst = $src">;
+  "setf.d $dst = $src">, isM;
 
 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
-  "getf.sig $dst = $src">;
+  "getf.sig $dst = $src">, isM;
 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
-  "setf.sig $dst = $src">;
+  "setf.sig $dst = $src">, isM;
 
 // these four FP<->int conversion patterns need checking/cleaning
 def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
@@ -678,11 +688,11 @@ def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
 
 let isTerminator = 1, isBranch = 1, noResults = 1 in {
   def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
-    "(p0) brl.cond.sptk $dst">;
+    "(p0) brl.cond.sptk $dst">, isB;
   def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
-    "($qp) brl.cond.sptk $dst">;
+    "($qp) brl.cond.sptk $dst">, isB;
   def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
-    "($qp) br.cond.sptk $dst">;
+    "($qp) br.cond.sptk $dst">, isB;
 }
 
 let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
@@ -703,29 +713,29 @@ let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
   out0,out1,out2,out3,out4,out5,out6,out7] in {
 // old pattern call
   def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
-  "br.call.sptk rp = $dst">;       // FIXME: teach llvm about branch regs?
+  "br.call.sptk rp = $dst">, isB;   // FIXME: teach llvm about branch regs?
 // new daggy stuff!  
 
 // calls a globaladdress
   def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst),
-  "br.call.sptk rp = $dst">;       // FIXME: teach llvm about branch regs?
+  "br.call.sptk rp = $dst">, isB;       // FIXME: teach llvm about branch regs?
 // calls an externalsymbol
   def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst),
-  "br.call.sptk rp = $dst">;       // FIXME: teach llvm about branch regs?
+  "br.call.sptk rp = $dst">, isB;       // FIXME: teach llvm about branch regs?
 // calls through a function descriptor
   def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg),
-  "br.call.sptk rp = $branchreg">; // FIXME: teach llvm about branch regs?
+  "br.call.sptk rp = $branchreg">, isB; // FIXME: teach llvm about branch regs?
   def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
-    "($qp) brl.cond.call.sptk $dst">;
+    "($qp) brl.cond.call.sptk $dst">, isB;
   def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
-    "($qp) br.cond.call.sptk $dst">;
+    "($qp) br.cond.call.sptk $dst">, isB;
 }
 
 // Return branch:
 let isTerminator = 1, isReturn = 1, noResults = 1 in
   def RET : AForm_DAG<0x03, 0x0b, (ops),
             "br.ret.sptk.many rp",
-            [(retflag)]>; // return
+            [(retflag)]>, isB; // return
 def : Pat<(ret), (RET)>;
 
 // the evil stop bit of despair