From: Eric Christopher <echristo@apple.com>
Date: Tue, 24 Aug 2010 01:10:04 +0000 (+0000)
Subject: Fix the opcode and the operands for the load instruction.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2012c7bb7be28c163a4b8034e961ace51f6a7224;p=oota-llvm.git

Fix the opcode and the operands for the load instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 2247b8549e0..a1b9eb480ce 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -415,10 +415,13 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
   } 
   
   // FIXME: There is more than one register class in the world...
+  // TODO: Verify the additions above work, otherwise we'll need to add the
+  // offset instead of 0 and do all sorts of operand munging.
   unsigned ResultReg = createResultReg(FixedRC);
+  unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR;
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                          TII.get(ARM::LDR), ResultReg)
-                  .addImm(0).addReg(Reg).addImm(Offset));
+                          TII.get(Opc), ResultReg)
+                  .addReg(Reg).addReg(0).addImm(0));
   UpdateValueMap(I, ResultReg);
         
   return true;