From: Chris Lattner Date: Tue, 7 Mar 2006 07:14:55 +0000 (+0000) Subject: add some new instructions to the classifier. With this, we correctly insert X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2046371e70e90d4435fcdf1b2ebeb64a2e5b2626;p=oota-llvm.git add some new instructions to the classifier. With this, we correctly insert a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26590 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 1b1559546b2..4408e950355 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -41,6 +41,7 @@ using namespace llvm; // conditions, we insert no-op instructions when appropriate. // // FIXME: This is missing some significant cases: +// -1. Handle all of the instruction types in GetInstrType. // 0. Handling of instructions that must be the first/last in a group. // 1. Modeling of microcoded instructions. // 2. Handling of cracked instructions. @@ -76,12 +77,18 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode) { case PPC::BLA: return BR; case PPC::LFS: + case PPC::LFD: case PPC::LWZ: + case PPC::LFSX: + case PPC::LWZX: return LSU_LD; case PPC::STFD: + case PPC::STW: return LSU_ST; case PPC::FADDS: case PPC::FCTIWZ: + case PPC::FRSP: + case PPC::FSUB: return FPU; } @@ -159,8 +166,11 @@ getHazardType(SDNode *Node) { unsigned LoadSize; switch (Opcode) { default: assert(0 && "Unknown load!"); + case PPC::LFSX: case PPC::LFS: + case PPC::LWZX: case PPC::LWZ: LoadSize = 4; break; + case PPC::LFD: LoadSize = 8; break; } if (isLoadOfStoredAddress(LoadSize, @@ -186,6 +196,7 @@ void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) { switch (Opcode) { default: assert(0 && "Unknown store instruction!"); case PPC::STFD: StoreSize = 8; break; + case PPC::STW: StoreSize = 4; break; } }