From: Ben Widawsky Date: Sat, 5 May 2012 01:58:59 +0000 (-0700) Subject: drm/i915: set IDICOS to medium uncore resources X-Git-Tag: firefly_0821_release~3680^2~2339^2~42^2~27 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=208482232de3590cee4757dfabe5d8cee8c6e626;p=firefly-linux-kernel-4.4.55.git drm/i915: set IDICOS to medium uncore resources I'm seeing about a 5% FPS improvement across various benchmarks on my IVB i3. Rumor has it that the higher end parts show even more benefit. This derives from a patch originally given to me by Bernard. The docs are confusing about the definition names (ie. medium really seems like max), but it would seem it gives more cache to the GT at the expense of uncore. This configuration makes the split most in favor of the GT. I've not tried the other IDICOS values. Cc: "Kilarski, Bernard R" Acked-by: Eric Anholt Signed-off-by: Ben Widawsky Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b7de5ea62aa4..404b474eaea3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3384,6 +3384,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int pipe; uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; + uint32_t snpcr; I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); @@ -3429,6 +3430,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) /* WaDisable4x2SubspanOptimization */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); + + snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); + snpcr &= ~GEN6_MBC_SNPCR_MASK; + snpcr |= GEN6_MBC_SNPCR_MED; + I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); } static void valleyview_init_clock_gating(struct drm_device *dev)