From: Boris BREZILLON <boris.brezillon@free-electrons.com>
Date: Tue, 13 May 2014 14:03:03 +0000 (+0200)
Subject: ARM: sunxi: dt: declare the r_pio pin controller for A31 SoC
X-Git-Tag: firefly_0821_release~176^2~3465^2~44^2~11^2~8
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=209394aed532c5de9bf549f4beac92bf1b80f887;p=firefly-linux-kernel-4.4.55.git

ARM: sunxi: dt: declare the r_pio pin controller for A31 SoC

The A31 SoC has a different pin controller for PL and PM banks.
Define this new controller in the device tree.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 90398fa1d0e5..2ad880c0821d 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -734,5 +734,19 @@
 			compatible = "allwinner,sun6i-a31-cpuconfig";
 			reg = <0x01f01c00 0x300>;
 		};
+
+		r_pio: pinctrl@01f02c00 {
+			compatible = "allwinner,sun6i-a31-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <0 45 4>,
+				     <0 46 4>;
+			clocks = <&apb0_gates 0>;
+			resets = <&apb0_rst 0>;
+			gpio-controller;
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+		};
 	};
 };