From: Colin LeMahieu <colinl@codeaurora.org>
Date: Thu, 11 Dec 2014 17:08:21 +0000 (+0000)
Subject: [Hexagon] Ading i64 <- i32, i32 sextw pattern.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=21876d5dd5b70bfe4766356f2cb97a12e80eb9ba;p=oota-llvm.git

[Hexagon] Ading i64 <- i32, i32 sextw pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224027 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index c936390d158..66b3412b934 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -2226,6 +2226,8 @@ class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
 let isCodeGenOnly = 0 in
 def A2_sxtw   : T_S2op_1_di <"sxtw", 0b01, 0b000>;
 
+def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
+
 //===----------------------------------------------------------------------===//
 // STYPE/ALU -
 //===----------------------------------------------------------------------===//