From: Colin LeMahieu Date: Thu, 18 Jun 2015 20:43:50 +0000 (+0000) Subject: [Hexagon] Printing packet brackets when asm printing and adding a number of tests... X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=21e6bede1291d5f94464f4b86d11e48a9160c52c;p=oota-llvm.git [Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240051 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 4e7bca634e3..bf6fb14dcca 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -11,9 +11,10 @@ // //===----------------------------------------------------------------------===// +#include "HexagonMCTargetDesc.h" +#include "Hexagon.h" #include "HexagonMCAsmInfo.h" #include "HexagonMCELFStreamer.h" -#include "HexagonMCTargetDesc.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" @@ -58,6 +59,57 @@ createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return X; } +namespace { +class HexagonTargetAsmStreamer : public HexagonTargetStreamer { + MCContext &Ctx; + formatted_raw_ostream &OS; + bool isVerboseAsm; + MCInstPrinter &IP; +public: + HexagonTargetAsmStreamer(MCStreamer &S, + formatted_raw_ostream &OS, bool isVerboseAsm, + MCInstPrinter &IP) + : HexagonTargetStreamer(S), Ctx(Ctx), OS(OS), isVerboseAsm(isVerboseAsm), + IP(IP) {} + MCStreamer &getStreamer() { return Streamer; } + void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS, + const MCInst &Inst, const MCSubtargetInfo &STI) override { + assert(HexagonMCInstrInfo::isBundle(Inst)); + assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE); + std::string Buffer; + { + raw_string_ostream TempStream(Buffer); + InstPrinter.printInst(&Inst, TempStream, "", STI); + } + StringRef Contents(Buffer); + auto PacketBundle = Contents.rsplit('\n'); + auto HeadTail = PacketBundle.first.split('\n'); + auto Preamble = "\t{\n\t\t"; + auto Separator = ""; + while(!HeadTail.first.empty()) { + OS << Separator; + StringRef Inst; + auto Duplex = HeadTail.first.split('\v'); + if(!Duplex.second.empty()){ + OS << Duplex.first << "\n"; + Inst = Duplex.second; + } + else { + if(!HeadTail.first.startswith("immext")) + Inst = Duplex.first; + } + OS << Preamble; + OS << Inst; + HeadTail = HeadTail.second.split('\n'); + Preamble = ""; + Separator = "\n\t\t"; + } + if(HexagonMCInstrInfo::bundleSize(Inst) != 0) + OS << "\n\t}" << PacketBundle.second; + } +}; +} + namespace { class HexagonTargetELFStreamer : public HexagonTargetStreamer { public: @@ -126,6 +178,12 @@ static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, return nullptr; } +MCTargetStreamer *createMCAsmTargetStreamer( + MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, + bool IsVerboseAsm) { + return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint); +} + static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { @@ -169,6 +227,10 @@ extern "C" void LLVMInitializeHexagonTargetMC() { // Register the obj streamer TargetRegistry::RegisterELFStreamer(TheHexagonTarget, createMCStreamer); + // Register the asm streamer + TargetRegistry::RegisterAsmTargetStreamer(TheHexagonTarget, + createMCAsmTargetStreamer); + // Register the MC Inst Printer TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget, createHexagonMCInstPrinter); diff --git a/test/CodeGen/Hexagon/always-ext.ll b/test/CodeGen/Hexagon/always-ext.ll index 3e8640fd34b..3bf465b6a51 100644 --- a/test/CodeGen/Hexagon/always-ext.ll +++ b/test/CodeGen/Hexagon/always-ext.ll @@ -4,9 +4,11 @@ ; due to a store that has a must-extend operand. ; CHECK: CuSuiteAdd.exit.us +; CHECK: { ; CHECK-NOT: call abort ; CHECK: memw(##0) ; CHECK: memw(r{{[0-9+]}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##4) +; CHECK: } %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* } %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112 = type { i32, [1024 x %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*], i32 } diff --git a/test/CodeGen/Hexagon/bugAsmHWloop.ll b/test/CodeGen/Hexagon/bugAsmHWloop.ll new file mode 100644 index 00000000000..c7e95ed0566 --- /dev/null +++ b/test/CodeGen/Hexagon/bugAsmHWloop.ll @@ -0,0 +1,71 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; CHECK: { +; CHECK: loop0(.LBB +; CHECK-NOT: loop0(##.LBB + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define i32 @q6zip_uncompress(i8* %out_buf, i32* %out_buf_size, i8* %in_buf, i32 %in_buf_size, i8* nocapture %dict, i32 %dict_size) nounwind { +entry: + %0 = bitcast i8* %in_buf to i32* + %incdec.ptr = getelementptr inbounds i8, i8* %in_buf, i32 4 + %1 = load i32, i32* %0, align 4, !tbaa !0 + %2 = ptrtoint i8* %incdec.ptr to i32 + %and.i = and i32 %2, 31 + %sub.i = sub i32 %2, %and.i + %3 = inttoptr i32 %sub.i to i8* + %add.i = add i32 %in_buf_size, 31 + %sub2.i = add i32 %add.i, %and.i + %div.i = lshr i32 %sub2.i, 5 + %4 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 32, i32 %div.i) nounwind + %5 = tail call i64 @llvm.hexagon.A4.combineir(i32 32, i32 %4) nounwind + tail call void asm sideeffect "l2fetch($0,$1)", "r,r,~{memory}"(i8* %3, i64 %5) nounwind, !srcloc !3 + %6 = ptrtoint i8* %out_buf to i32 + br label %for.body.i + +for.body.i: ; preds = %for.body.i, %entry + %i.02.i = phi i32 [ 0, %entry ], [ %inc.i, %for.body.i ] + %addr.addr.01.i = phi i32 [ %6, %entry ], [ %add.i14, %for.body.i ] + tail call void asm sideeffect "dczeroa($0)", "r"(i32 %addr.addr.01.i) nounwind, !srcloc !4 + %add.i14 = add i32 %addr.addr.01.i, 32 + %inc.i = add i32 %i.02.i, 1 + %exitcond.i = icmp eq i32 %inc.i, 128 + br i1 %exitcond.i, label %while.cond.preheader, label %for.body.i + +while.cond.preheader: ; preds = %for.body.i + %and = and i32 %1, 3 + switch i32 %and, label %infloop.preheader [ + i32 0, label %exit_inflate.split + i32 2, label %if.then.preheader + ] + +if.then.preheader: ; preds = %while.cond.preheader + br label %if.then + +infloop.preheader: ; preds = %while.cond.preheader + br label %infloop + +if.then: ; preds = %if.then.preheader, %if.then + tail call void @llvm.prefetch(i8* %incdec.ptr, i32 0, i32 3, i32 1) + br label %if.then + +exit_inflate.split: ; preds = %while.cond.preheader + ret i32 0 + +infloop: ; preds = %infloop.preheader, %infloop + br label %infloop +} + +declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind + +declare i64 @llvm.hexagon.A4.combineir(i32, i32) nounwind readnone + +declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) nounwind readnone + +!0 = !{!"long", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} +!3 = !{i32 18362} +!4 = !{i32 18893} diff --git a/test/CodeGen/Hexagon/cext-valid-packet1.ll b/test/CodeGen/Hexagon/cext-valid-packet1.ll index 35e7b364b50..36abc59f5e3 100644 --- a/test/CodeGen/Hexagon/cext-valid-packet1.ll +++ b/test/CodeGen/Hexagon/cext-valid-packet1.ll @@ -1,5 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; XFAIL: +; RUN: llc -march=hexagon < %s | FileCheck %s ; Check that the packetizer generates valid packets with constant ; extended instructions. diff --git a/test/CodeGen/Hexagon/cext-valid-packet2.ll b/test/CodeGen/Hexagon/cext-valid-packet2.ll index c3a4915ec2e..9f03ef1309e 100644 --- a/test/CodeGen/Hexagon/cext-valid-packet2.ll +++ b/test/CodeGen/Hexagon/cext-valid-packet2.ll @@ -1,44 +1,16 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; XFAIL: +; RUN: llc -march=hexagon < %s | FileCheck %s ; Check that the packetizer generates valid packets with constant ; extended add and base+offset store instructions. -; CHECK: { -; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}}) -; CHECK-NEXT: memw(r{{[0-9]+}}+{{ *}}##{{[0-9]+}}){{ *}}={{ *}}r{{[0-9]+}}.new +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}},{{ *}}##200000) +; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}##12000){{ *}}={{ *}}r{{[0-9]+}}.new ; CHECK-NEXT: } -define i32 @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind { +define void @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind { entry: - %add = add nsw i32 %c, 200002 %0 = load i32, i32* %a, align 4 %add1 = add nsw i32 %0, 200000 %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 3000 store i32 %add1, i32* %arrayidx2, align 4 - %1 = load i32, i32* %b, align 4 - %add4 = add nsw i32 %1, 200001 - %arrayidx5 = getelementptr inbounds i32, i32* %a, i32 1 - store i32 %add4, i32* %arrayidx5, align 4 - %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 1 - %2 = load i32, i32* %arrayidx7, align 4 - %cmp = icmp sgt i32 %add4, %2 - br i1 %cmp, label %if.then, label %if.else - -if.then: ; preds = %entry - %arrayidx8 = getelementptr inbounds i32, i32* %a, i32 2 - %3 = load i32, i32* %arrayidx8, align 4 - %arrayidx9 = getelementptr inbounds i32, i32* %b, i32 2000 - %4 = load i32, i32* %arrayidx9, align 4 - %sub = sub nsw i32 %3, %4 - %arrayidx10 = getelementptr inbounds i32, i32* %a, i32 4000 - store i32 %sub, i32* %arrayidx10, align 4 - br label %if.end - -if.else: ; preds = %entry - %arrayidx11 = getelementptr inbounds i32, i32* %b, i32 3200 - store i32 %add, i32* %arrayidx11, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - ret i32 %add + ret void } diff --git a/test/CodeGen/Hexagon/checktabs.ll b/test/CodeGen/Hexagon/checktabs.ll new file mode 100644 index 00000000000..740433bf824 --- /dev/null +++ b/test/CodeGen/Hexagon/checktabs.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck --strict-whitespace %s +; Make sure we are emitting tabs as formatting. +; CHECK: { +; CHECK-NEXT: {{jump|r}} +define i32 @foobar(i32 %a, i32 %b) { + %1 = add i32 %a, %b + ret i32 %1 +} diff --git a/test/CodeGen/Hexagon/eh_return.ll b/test/CodeGen/Hexagon/eh_return.ll new file mode 100644 index 00000000000..67649a07afc --- /dev/null +++ b/test/CodeGen/Hexagon/eh_return.ll @@ -0,0 +1,48 @@ +; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; Make sure we generate an exception handling return. + +; CHECK: deallocframe +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r29 = add(r29, r28) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: jumpr r31 +; CHECK-NEXT: } + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +%struct.Data = type { i32, i8* } + +define i32 @test_eh_return(i32 %a, i32 %b) nounwind { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + %d = alloca %struct.Data, align 4 + store i32 %a, i32* %a.addr, align 4 + store i32 %b, i32* %b.addr, align 4 + %0 = load i32, i32* %a.addr, align 4 + %1 = load i32, i32* %b.addr, align 4 + %cmp = icmp sgt i32 %0, %1 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + %2 = load i32, i32* %a.addr, align 4 + %3 = load i32, i32* %b.addr, align 4 + %add = add nsw i32 %2, %3 + ret i32 %add + +if.else: ; preds = %entry + %call = call i32 @setup(%struct.Data* %d) + %_d1 = getelementptr inbounds %struct.Data, %struct.Data* %d, i32 0, i32 0 + %4 = load i32, i32* %_d1, align 4 + %_d2 = getelementptr inbounds %struct.Data, %struct.Data* %d, i32 0, i32 1 + %5 = load i8*, i8** %_d2, align 4 + call void @llvm.eh.return.i32(i32 %4, i8* %5) + unreachable +} + +declare i32 @setup(%struct.Data*) + +declare void @llvm.eh.return.i32(i32, i8*) nounwind diff --git a/test/CodeGen/Hexagon/postinc-offset.ll b/test/CodeGen/Hexagon/postinc-offset.ll new file mode 100644 index 00000000000..5e0f4751f30 --- /dev/null +++ b/test/CodeGen/Hexagon/postinc-offset.ll @@ -0,0 +1,40 @@ +; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; CHECK: { +; CHECK: ={{ *}}memd([[REG0:(r[0-9]+)]]{{ *}}++{{ *}}#8) +; CHECK-NOT: memw([[REG0]]{{ *}}+{{ *}}#0){{ *}}= +; CHECK: } + +define void @main() #0 { +cond.end.6: + store i32 -1, i32* undef, align 8, !tbaa !0 + br label %polly.stmt.for.body.i + +if.then: + unreachable + +if.end: + ret void + +polly.stmt.for.body.i24: + %0 = extractelement <2 x i32> %add.ip_vec, i32 1 + br i1 undef, label %if.end, label %if.then + +polly.stmt.for.body.i: + %add.ip_vec30 = phi <2 x i32> [ %add.ip_vec, %polly.stmt.for.body.i ], [ zeroinitializer, %cond.end.6 ] + %scevgep.phi = phi i32* [ %scevgep.inc, %polly.stmt.for.body.i ], [ undef, %cond.end.6 ] + %polly.indvar = phi i32 [ %polly.indvar_next, %polly.stmt.for.body.i ], [ 0, %cond.end.6 ] + %vector_ptr = bitcast i32* %scevgep.phi to <2 x i32>* + %_p_vec_full = load <2 x i32>, <2 x i32>* %vector_ptr, align 8 + %add.ip_vec = add <2 x i32> %_p_vec_full, %add.ip_vec30 + %polly.indvar_next = add nsw i32 %polly.indvar, 2 + %polly.loop_cond = icmp slt i32 %polly.indvar, 4 + %scevgep.inc = getelementptr i32, i32* %scevgep.phi, i32 2 + br i1 %polly.loop_cond, label %polly.stmt.for.body.i, label %polly.stmt.for.body.i24 +} + +attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!0 = !{!"int", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/usr-ovf-dep.ll b/test/CodeGen/Hexagon/usr-ovf-dep.ll new file mode 100644 index 00000000000..1f06986f0aa --- /dev/null +++ b/test/CodeGen/Hexagon/usr-ovf-dep.ll @@ -0,0 +1,28 @@ +; RUN: llc -O2 < %s | FileCheck %s +target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" +target triple = "hexagon" + +; Check that the two ":sat" instructions are in the same packet. +; CHECK: foo +; CHECK: { +; CHECK: :sat +; CHECK-NEXT: :sat + +target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" +target triple = "hexagon" + +; Function Attrs: nounwind readnone +define i32 @foo(i32 %Rs, i32 %Rt, i32 %Ru) #0 { +entry: + %0 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rs, i32 %Ru) + %1 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rt, i32 %Ru) + %add = add nsw i32 %1, %0 + ret i32 %add +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1 + +attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } +