From: dkl <dkl@rock-chips.com>
Date: Tue, 24 Jun 2014 10:00:38 +0000 (+0800)
Subject: clk: rk3288: modify RK3288_LIMIT_PLL_VIO0/1
X-Git-Tag: firefly_0821_release~5051
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=22bab315d1f002334ebbc1dc3998c5d13ef42ab8;p=firefly-linux-kernel-4.4.55.git

clk: rk3288: modify RK3288_LIMIT_PLL_VIO0/1

This commit corresponds to commit debf1d2237185a26503d737d54db730f62cf5ea5.
---

diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 3417e27769b0..7107134a8e7e 100644
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -558,7 +558,7 @@ const struct clk_ops clkops_rate_3288_usb480m = {
 	.recalc_rate	= clk_3288_usb480m_recalc_rate,
 };
 
-#define RK3288_LIMIT_PLL_VIO0 (400*MHZ)
+#define RK3288_LIMIT_PLL_VIO0 (410*MHZ)
 
 static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long rate,
 		unsigned long *best_parent_rate,
@@ -619,7 +619,7 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc0 = {
 	.recalc_rate	= clk_divider_recalc_rate,
 };
 
-#define RK3288_LIMIT_PLL_VIO1 (410*MHZ)
+#define RK3288_LIMIT_PLL_VIO1 (350*MHZ)
 
 static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long rate,
 		unsigned long *best_parent_rate,