From: Akira Hatanaka Date: Thu, 20 Dec 2012 03:34:05 +0000 (+0000) Subject: [mips] Refactor arithmetic and logic instructions. Separate encoding X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=23a3da0113600a2c3204f766cbc51d68a8ed4d94;p=oota-llvm.git [mips] Refactor arithmetic and logic instructions. Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 26ade789dc1..dde7bc65bfb 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -94,15 +94,15 @@ def XORi64 : ArithLogicI<0x0e, "xori", uimm16_64, immZExt16, CPU64Regs, xor>; def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; /// Arithmetic Instructions (3-Operand, R-Type) -def DADD : ArithLogicR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>; -def DADDu : ArithLogicR<0x00, 0x2d, "daddu", IIAlu, CPU64Regs, 1, add>; -def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", IIAlu, CPU64Regs, 0, sub>; -def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; -def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; -def AND64 : ArithLogicR<0x00, 0x24, "and", IIAlu, CPU64Regs, 1, and>; -def OR64 : ArithLogicR<0x00, 0x25, "or", IIAlu, CPU64Regs, 1, or>; -def XOR64 : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPU64Regs, 1, xor>; -def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; +def DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>; +def DADDu : ArithLogicR<"daddu", IIAlu, CPU64Regs, 1, add>, ADD_FM<0, 0x2d>; +def DSUBu : ArithLogicR<"dsubu", IIAlu, CPU64Regs, 0, sub>, ADD_FM<0, 0x2f>; +def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; +def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; +def AND64 : ArithLogicR<"and", IIAlu, CPU64Regs, 1, and>, ADD_FM<0, 0x24>; +def OR64 : ArithLogicR<"or", IIAlu, CPU64Regs, 1, or>, ADD_FM<0, 0x25>; +def XOR64 : ArithLogicR<"xor", IIAlu, CPU64Regs, 1, xor>, ADD_FM<0, 0x26>; +def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; /// Shift Instructions def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>; diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 986580bf9f8..071764b645e 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -192,6 +192,21 @@ class MFC3OP op, bits<5> _mfmt, dag outs, dag ins, string asmstr>: let Inst{2-0} = sel; } +class ADD_FM op, bits<6> funct> { + bits<5> rd; + bits<5> rs; + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = op; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-6} = 0; + let Inst{5-0} = funct; +} + //===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index f8ebabf8547..9a3c9133a2c 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -345,13 +345,11 @@ def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; // Arithmetic and logical instructions with 3 register operands. -class ArithLogicR op, bits<6> func, string instr_asm, - InstrItinClass itin, RegisterClass RC, bit isComm = 0, - SDPatternOperator OpNode = null_frag>: - FR { - let shamt = 0; +class ArithLogicR: + InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), + !strconcat(opstr, "\t$rd, $rs, $rt"), + [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { let isCommutable = isComm; let isReMaterializable = 1; } @@ -930,16 +928,16 @@ def XORi : ArithLogicI<0x0e, "xori", uimm16, immZExt16, CPURegs, xor>; def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; /// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : ArithLogicR<0x00, 0x21, "addu", IIAlu, CPURegs, 1, add>; -def SUBu : ArithLogicR<0x00, 0x23, "subu", IIAlu, CPURegs, 0, sub>; -def ADD : ArithLogicR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; -def SUB : ArithLogicR<0x00, 0x22, "sub", IIAlu, CPURegs, 0>; -def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; -def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; -def AND : ArithLogicR<0x00, 0x24, "and", IIAlu, CPURegs, 1, and>; -def OR : ArithLogicR<0x00, 0x25, "or", IIAlu, CPURegs, 1, or>; -def XOR : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPURegs, 1, xor>; -def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; +def ADDu : ArithLogicR<"addu", IIAlu, CPURegs, 1, add>, ADD_FM<0, 0x21>; +def SUBu : ArithLogicR<"subu", IIAlu, CPURegs, 0, sub>, ADD_FM<0, 0x23>; +def ADD : ArithLogicR<"add", IIAlu, CPURegs, 1>, ADD_FM<0, 0x20>; +def SUB : ArithLogicR<"sub", IIAlu, CPURegs, 0>, ADD_FM<0, 0x22>; +def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; +def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; +def AND : ArithLogicR<"and", IIAlu, CPURegs, 1, and>, ADD_FM<0, 0x24>; +def OR : ArithLogicR<"or", IIAlu, CPURegs, 1, or>, ADD_FM<0, 0x25>; +def XOR : ArithLogicR<"xor", IIAlu, CPURegs, 1, xor>, ADD_FM<0, 0x26>; +def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; /// Shift Instructions def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; @@ -1063,8 +1061,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>; // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. -def MUL : ArithLogicR<0x1c, 0x02, "mul", IIImul, CPURegs, 1, mul>, - Requires<[HasStdEnc]>; +def MUL : ArithLogicR<"mul", IIImul, CPURegs, 1, mul>, ADD_FM<0x1c, 0x02>; def RDHWR : ReadHardware;