From: Frank Wang <frank.wang@rock-chips.com>
Date: Mon, 8 May 2017 07:23:40 +0000 (+0800)
Subject: arm: dts: add watchdog and uart2 related for rk322x SoC
X-Git-Tag: release-20171130_firefly~4^2~633
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=23de1f8c341f745496b8f98e9d0818b3d0d88165;p=firefly-linux-kernel-4.4.55.git

arm: dts: add watchdog and uart2 related for rk322x SoC

Add another GPIO sets for UART2 since the old ones are conflict
with SDMMC, also add watchdog support.

Change-Id: Ib0f1472b9a7760e15e1b83e103f65f43e3642643
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---

diff --git a/arch/arm/boot/dts/rk322x-android.dtsi b/arch/arm/boot/dts/rk322x-android.dtsi
index 3fcc30606bb5..6729dbe7973a 100644
--- a/arch/arm/boot/dts/rk322x-android.dtsi
+++ b/arch/arm/boot/dts/rk322x-android.dtsi
@@ -55,7 +55,7 @@
 		rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
 		rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
 		pinctrl-names = "default";
-		pinctrl-0 = <&uart2_xfer>;
+		pinctrl-0 = <&uart21_xfer>;
 	};
 
 	psci {
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 4da3d8b2600e..b33bdddbe067 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -266,7 +266,7 @@
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
 		pinctrl-names = "default";
-		pinctrl-0 = <&uart2_xfer>;
+		pinctrl-0 = <&uart21_xfer>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		status = "disabled";
@@ -324,6 +324,14 @@
 		status = "disabled";
 	};
 
+	wdt: watchdog@110a0000 {
+		compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
+		reg = <0x110a0000 0x100>;
+		clocks = <&cru PCLK_CPU>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
 	pwm0: pwm@110b0000 {
 		compatible = "rockchip,rk3288-pwm";
 		reg = <0x110b0000 0x10>;
@@ -857,7 +865,7 @@
 
 		uart2 {
 			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
+				rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 						<1 19 RK_FUNC_2 &pcfg_pull_none>;
 			};
 
@@ -869,5 +877,12 @@
 				rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
+
+		uart2-1 {
+			uart21_xfer: uart21-xfer {
+				rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
+						<1 9 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
 	};
 };