From: Linus Walleij Date: Tue, 27 Nov 2012 19:15:20 +0000 (+0100) Subject: clk: ux500: fix bit error X-Git-Tag: firefly_0821_release~3680^2~1528^2~2 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2630b17b6ee47ac79b4f5120ac49105027f644ea;p=firefly-linux-kernel-4.4.55.git clk: ux500: fix bit error This fixes a bit error in the U8500 clock implementation: the unused p2_pclk12 registered at bit 12 in periphereral group 6 was defined as using bit 11 rather than bit 12. When walking over and disabling the unused clocks in the tree at late init time, p2_pclk12 was disabled, by effectively clearing the but for p2_pclk11 instead of bit 12 as it should have, thus disabling gpio block 6 and 7. Reported-by: Lee Jones Acked-by: Ulf Hansson Cc: Philippe Begnic Cc: stable@kernel.org Signed-off-by: Linus Walleij Signed-off-by: Mike Turquette --- diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 64877e1588e4..7d0e0258f204 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -326,7 +326,7 @@ void u8500_clk_init(void) clk_register_clkdev(clk, NULL, "gpioblock1"); clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, - BIT(11), 0); + BIT(12), 0); clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0);