From: xxx <xxx@rock-chips.com>
Date: Mon, 6 May 2013 09:45:58 +0000 (+0800)
Subject: edit div_clk_for_pll_int
X-Git-Tag: firefly_0821_release~7156
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2856fc4998b403a86b1b9fbe45d2bf609f924c25;p=firefly-linux-kernel-4.4.55.git

edit div_clk_for_pll_int
---

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index eaddf6096364..5a43df76eb68 100755
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -3424,7 +3424,6 @@ static int pll_get_flag(void)
 
 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
 {
-	div_clk_for_pll_init();
 	//general
 	clk_set_rate_nolock(&general_pll_clk, gpll_rate);
 	//code pll
@@ -3534,6 +3533,8 @@ void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int fl
 #endif
 		clk_register(lk->clk);
 	}
+	
+	div_clk_for_pll_init();
 	clk_recalculate_root_clocks_nolock();
 
 	loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);