From: Huang, Tao Date: Tue, 16 Dec 2014 12:55:58 +0000 (+0800) Subject: Revert "rk32 dp: port to rk3368" X-Git-Tag: firefly_0821_release~4158^2~511 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2920ad6c0dc527779bb0fdb911a042efb3d5cacc;p=firefly-linux-kernel-4.4.55.git Revert "rk32 dp: port to rk3368" This reverts commit b8fdfeb2cfeec753b23236584e9e24b1f3be83c1. --- diff --git a/arch/arm64/boot/dts/rk3368-tb_8846.dts b/arch/arm64/boot/dts/rk3368-tb_8846.dts old mode 100755 new mode 100644 index 3aa5318ece42..54ce3ed72195 --- a/arch/arm64/boot/dts/rk3368-tb_8846.dts +++ b/arch/arm64/boot/dts/rk3368-tb_8846.dts @@ -3,8 +3,7 @@ #include #include #include "rk3368.dtsi" -//#include "../../../arm/boot/dts/lcd-b101ew05.dtsi" -#include "../../../arm/boot/dts/lcd-F402.dtsi" +#include "../../../arm/boot/dts/lcd-b101ew05.dtsi" / { chosen { diff --git a/arch/arm64/boot/dts/rk3368.dtsi b/arch/arm64/boot/dts/rk3368.dtsi index 9016b4dd8eca..27137ef901d6 100644 --- a/arch/arm64/boot/dts/rk3368.dtsi +++ b/arch/arm64/boot/dts/rk3368.dtsi @@ -644,8 +644,7 @@ edp: edp@ff970000 { compatible = "rockchip,rk32-edp"; reg = <0x0 0xff970000 0x0 0x4000>; - rockchip,grf = <&grf>; - interrupts = ; + interrupts = ; clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>; clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; }; diff --git a/drivers/video/rockchip/transmitter/rk32_dp.c b/drivers/video/rockchip/transmitter/rk32_dp.c index 3a75c0f635b1..51461f1af80b 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp.c +++ b/drivers/video/rockchip/transmitter/rk32_dp.c @@ -12,20 +12,20 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include -#include -#include +#include +#include #include +#include +#include +#include +#include #include -#include -#include +#include #include -#include +#include #include #include -#include -#include -#include +#include "rk32_dp.h" #if defined(CONFIG_OF) #include @@ -37,27 +37,16 @@ #include #endif -#include "rk32_dp.h" - /*#define EDP_BIST_MODE*/ /*#define SW_LT*/ - -#define RK3368_GRF_SOC_CON4 0x410 - static struct rk32_edp *rk32_edp; static int rk32_edp_clk_enable(struct rk32_edp *edp) { - int ret; - if (!edp->clk_on) { - // clk_prepare_enable(edp->pd); + clk_prepare_enable(edp->pd); clk_prepare_enable(edp->pclk); clk_prepare_enable(edp->clk_edp); - ret = clk_set_rate(edp->clk_24m, 24000000); - if (ret < 0) - dev_err(edp->dev, - "cannot set edp clk_24m %d\n", ret); clk_prepare_enable(edp->clk_24m); edp->clk_on = true; } @@ -71,42 +60,30 @@ static int rk32_edp_clk_disable(struct rk32_edp *edp) clk_disable_unprepare(edp->pclk); clk_disable_unprepare(edp->clk_edp); clk_disable_unprepare(edp->clk_24m); - //clk_disable_unprepare(edp->pd); + clk_disable_unprepare(edp->pd); edp->clk_on = false; } return 0; } -static int rk32_edp_pre_init(struct rk32_edp *edp) +static int rk32_edp_pre_init(void) { u32 val; - - if (cpu_is_rk3288()) { - val = GRF_EDP_REF_CLK_SEL_INTER | (GRF_EDP_REF_CLK_SEL_INTER << 16); - writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12); - - val = 0x80008000; - writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/ - dsb(sy); - udelay(1); - val = 0x80000000; - writel_relaxed(val, RK_CRU_VIRT + 0x01d0); - dsb(sy); - udelay(1); - } else { - val = 0x01 | (0x01 << 16); - regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val); - - val = 0x80008000; - regmap_write(edp->grf, 0x318, val); /*reset edp*/ - dsb(sy); - udelay(1); - val = 0x80000000; - regmap_write(edp->grf, 0x318, val); - dsb(sy); - udelay(1); - } + val = GRF_EDP_REF_CLK_SEL_INTER | (GRF_EDP_REF_CLK_SEL_INTER << 16); + writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12); + + val = 0x80008000; + writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/ + dsb(); + val = 0x80008000; + writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/ + dsb(); + udelay(1); + val = 0x80000000; + writel_relaxed(val, RK_CRU_VIRT + 0x01d0); + dsb(); + udelay(1); return 0; } @@ -116,14 +93,11 @@ static int rk32_edp_init_edp(struct rk32_edp *edp) u32 val = 0; rk_fb_get_prmry_screen(screen); - - if (cpu_is_rk3288()) { - if (screen->lcdc_id == 1) /*select lcdc*/ - val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16); - else - val = EDP_SEL_VOP_LIT << 16; - writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6); - } + if (screen->lcdc_id == 1) /*select lcdc*/ + val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16); + else + val = EDP_SEL_VOP_LIT << 16; + writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6); rk32_edp_reset(edp); rk32_edp_init_refclk(edp); @@ -1179,7 +1153,7 @@ static int rk32_edp_enable(void) rk32_edp_clk_enable(edp); - rk32_edp_pre_init(edp); + rk32_edp_pre_init(); rk32_edp_init_edp(edp); enable_irq(edp->irq); /*ret = rk32_edp_handle_edid(edp); @@ -1378,12 +1352,6 @@ static int rk32_edp_probe(struct platform_device *pdev) return PTR_ERR(edp->regs); } - edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(edp->grf)) { - dev_err(&pdev->dev, "can't find rockchip,grf property\n"); - return PTR_ERR(edp->grf); - } - edp->pd = devm_clk_get(&pdev->dev, "pd_edp"); if (IS_ERR(edp->pd)) dev_err(&pdev->dev, "cannot get pd\n"); @@ -1406,7 +1374,7 @@ static int rk32_edp_probe(struct platform_device *pdev) } rk32_edp_clk_enable(edp); if (!support_uboot_display()) - rk32_edp_pre_init(edp); + rk32_edp_pre_init(); edp->irq = platform_get_irq(pdev, 0); if (edp->irq < 0) { dev_err(&pdev->dev, "cannot find IRQ\n"); diff --git a/drivers/video/rockchip/transmitter/rk32_dp.h b/drivers/video/rockchip/transmitter/rk32_dp.h index 8be685b3ae34..de90cf29dc45 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp.h +++ b/drivers/video/rockchip/transmitter/rk32_dp.h @@ -1,8 +1,5 @@ #ifndef __RK32_DP_H #define __RK32_DP_H - -#include -#include #include #include "dpcd_edid.h" @@ -516,7 +513,6 @@ struct link_train { struct rk32_edp { struct device *dev; void __iomem *regs; - struct regmap *grf; unsigned int irq; struct clk *pd; struct clk *clk_edp; /*clk for edp controller*/