From: Xing Zheng Date: Wed, 8 Jun 2016 07:18:27 +0000 (+0800) Subject: clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX X-Git-Tag: firefly_0821_release~2502 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2d06e17d84a2499fe88e247c496d8ec7f694f9e2;p=firefly-linux-kernel-4.4.55.git clk: rockchip: fix the rk3399 spdif incorrect bit for DPTX Change-Id: I46e8c54de7c74c1abb001512198176ee51b638ac Reported-by: Chris Zhong Tested-by: Chris Zhong Signed-off-by: Xing Zheng --- diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index dc7fe86b9fb4..b5a95d87888a 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -591,7 +591,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, - RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(10), 6, GFLAGS), /* i2s */ COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,