From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 14 Feb 2015 02:51:44 +0000 (+0000)
Subject: R600/SI: Fix size of VReg_1
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2d925cbe1095d9e79985b5770e051c5935ab333a;p=oota-llvm.git

R600/SI: Fix size of VReg_1

This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229223 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
index 3b0971b11ad..1a7811f86d6 100644
--- a/lib/Target/R600/SIRegisterInfo.td
+++ b/lib/Target/R600/SIRegisterInfo.td
@@ -209,7 +209,7 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256
 
 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
 
-def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>;
+def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
 
 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
   let OperandNamespace = "AMDGPU";