From: Chris Lattner <sabre@nondot.org>
Date: Wed, 12 Jan 2005 18:19:52 +0000 (+0000)
Subject: Fix sign extend to long.  When coming from sbyte, we used to generate:
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2dad454af674cb41a14a85ad6ce5c85c43959acd;p=oota-llvm.git

Fix sign extend to long.  When coming from sbyte, we used to generate:

        movsbl 4(%esp), %eax
        movl %eax, %edx
        sarl $7, %edx

Now we generate:

        movsbl 4(%esp), %eax
        movl %eax, %edx
        sarl $31, %edx

Which is right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19515 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f3b344bb8c1..64c686efc67 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -805,8 +805,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     
     // The high part is obtained by SRA'ing all but one of the bits of the lo
     // part.
-    unsigned SrcSize = MVT::getSizeInBits(Node->getOperand(0).getValueType());
-    Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(SrcSize-1, MVT::i8));
+    unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
+    Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, MVT::i8));
     break;
   }
   case ISD::ZERO_EXTEND: