From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 11 Oct 2006 07:10:22 +0000 (+0000)
Subject: Naming consistency.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2e49f090f9656af7d5ed4d5c4e9fa26af59c7233;p=oota-llvm.git

Naming consistency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30878 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 3ea20eab23b..45a01ac883e 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1383,8 +1383,8 @@ class LoadSDNode : public SDNode {
   // ExtType - non-ext, anyext, sext, zext.
   ISD::LoadExtType ExtType;
 
-  // LoadVT - VT of loaded value before extension.
-  MVT::ValueType LoadVT;
+  // LoadedVT - VT of loaded value before extension.
+  MVT::ValueType LoadedVT;
 
   // SrcValue - Memory location for alias analysis.
   const Value *SrcValue;
@@ -1403,7 +1403,7 @@ protected:
              ISD::MemOpAddrMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT,
              const Value *SV, int O=0, unsigned Align=1, bool Vol=false)
     : SDNode(ISD::LOAD, Chain, Ptr, Off),
-      AddrMode(AM), ExtType(ETy), LoadVT(LVT), SrcValue(SV), SVOffset(O),
+      AddrMode(AM), ExtType(ETy), LoadedVT(LVT), SrcValue(SV), SVOffset(O),
       Alignment(Align), IsVolatile(Vol) {
     assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
            "Only post-indexed load has a non-undef offset operand");
@@ -1412,7 +1412,7 @@ protected:
              ISD::LoadExtType ETy, MVT::ValueType LVT,
              const Value *SV, int O=0, unsigned Align=1, bool Vol=false)
     : SDNode(ISD::LOAD, Chain, Ptr, Off),
-      AddrMode(ISD::UNINDEXED), ExtType(ETy), LoadVT(LVT), SrcValue(SV),
+      AddrMode(ISD::UNINDEXED), ExtType(ETy), LoadedVT(LVT), SrcValue(SV),
       SVOffset(O), Alignment(Align), IsVolatile(Vol) {
     assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
            "Only post-indexed load has a non-undef offset operand");
@@ -1424,7 +1424,7 @@ public:
   const SDOperand getOffset() const { return getOperand(2); }
   ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; }
   ISD::LoadExtType getExtensionType() const { return ExtType; }
-  MVT::ValueType getLoadVT() const { return LoadVT; }
+  MVT::ValueType getLoadedVT() const { return LoadedVT; }
   const Value *getSrcValue() const { return SrcValue; }
   int getSrcValueOffset() const { return SVOffset; }
   unsigned getAlignment() const { return Alignment; }
@@ -1445,7 +1445,7 @@ class StoreSDNode : public SDNode {
   // IsTruncStore - True is the op does a truncation before store.
   bool IsTruncStore;
 
-  // StoreVT - VT of the value after truncation.
+  // StoredVT - VT of the value after truncation.
   MVT::ValueType StoredVT;
 
   // SrcValue - Memory location for alias analysis.
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 96456aa5f05..262b023c7ea 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1077,7 +1077,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
   // fold (zext_inreg (extload x)) -> (zextload x)
   if (ISD::isEXTLoad(N0.Val)) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getLoadVT();
+    MVT::ValueType EVT = LN0->getLoadedVT();
     // If we zero all the possible extended bits, then we can turn this into
     // a zextload if we are running before legalize or the operation is legal.
     if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@@ -1093,7 +1093,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
   // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
   if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getLoadVT();
+    MVT::ValueType EVT = LN0->getLoadedVT();
     // If we zero all the possible extended bits, then we can turn this into
     // a zextload if we are running before legalize or the operation is legal.
     if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@@ -1123,7 +1123,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
       else
         EVT = MVT::Other;
     
-      LoadedVT = LN0->getLoadVT();
+      LoadedVT = LN0->getLoadedVT();
       if (EVT != MVT::Other && LoadedVT > EVT &&
           (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
         MVT::ValueType PtrType = N0.getOperand(1).getValueType();
@@ -1874,7 +1874,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
   if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getLoadVT();
+    MVT::ValueType EVT = LN0->getLoadedVT();
     SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
                                        LN0->getSrcValueOffset(), EVT);
@@ -1943,7 +1943,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
   if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getLoadVT();
+    MVT::ValueType EVT = LN0->getLoadedVT();
     SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
                                        LN0->getSrcValueOffset(), EVT);
@@ -2014,7 +2014,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
   if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
       N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    MVT::ValueType EVT = LN0->getLoadVT();
+    MVT::ValueType EVT = LN0->getLoadedVT();
     SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
                                        LN0->getChain(), LN0->getBasePtr(),
                                        LN0->getSrcValue(),
@@ -2069,7 +2069,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   
   // fold (sext_inreg (extload x)) -> (sextload x)
   if (ISD::isEXTLoad(N0.Val) && 
-      EVT == cast<LoadSDNode>(N0)->getLoadVT() &&
+      EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
       (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@@ -2081,7 +2081,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   }
   // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
   if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
-      EVT == cast<LoadSDNode>(N0)->getLoadVT() &&
+      EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
       (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@@ -3282,7 +3282,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
       LoadSDNode *RLD = cast<LoadSDNode>(RHS);
 
       // If this is an EXTLOAD, the VT's must match.
-      if (LLD->getLoadVT() == RLD->getLoadVT()) {
+      if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
         // FIXME: this conflates two src values, discarding one.  This is not
         // the right thing to do, but nothing uses srcvalues now.  When they do,
         // turn SrcValue into a list of locations.
@@ -3307,7 +3307,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
                                 TheSelect->getValueType(0),
                                 LLD->getChain(), Addr, LLD->getSrcValue(),
                                 LLD->getSrcValueOffset(),
-                                LLD->getLoadVT());
+                                LLD->getLoadedVT());
         }
         // Users of the select now use the result of the load.
         CombineTo(TheSelect, Load);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b7262d653f3..c0d3076fe1a 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1364,7 +1364,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
       return Op.ResNo ? Tmp4 : Tmp3;
     } else {
-      MVT::ValueType SrcVT = LD->getLoadVT();
+      MVT::ValueType SrcVT = LD->getLoadedVT();
       switch (TLI.getLoadXAction(ExtType, SrcVT)) {
       default: assert(0 && "This action is not supported yet!");
       case TargetLowering::Promote:
@@ -3228,7 +3228,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Result = DAG.getExtLoad(ExtType, NVT,
                             LD->getChain(), LD->getBasePtr(),
                             LD->getSrcValue(), LD->getSrcValueOffset(),
-                            LD->getLoadVT());
+                            LD->getLoadedVT());
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
@@ -4431,7 +4431,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
       if (!TLI.isLittleEndian())
         std::swap(Lo, Hi);
     } else {
-      MVT::ValueType EVT = LD->getLoadVT();
+      MVT::ValueType EVT = LD->getLoadedVT();
     
       if (EVT == NVT)
         Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f2e14231d4a..81473247e18 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -457,7 +457,7 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
   if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
     ID.AddInteger(LD->getAddressingMode());
     ID.AddInteger(LD->getExtensionType());
-    ID.AddInteger(LD->getLoadVT());
+    ID.AddInteger(LD->getLoadedVT());
     ID.AddPointer(LD->getSrcValue());
     ID.AddInteger(LD->getSrcValueOffset());
     ID.AddInteger(LD->getAlignment());
@@ -2715,7 +2715,7 @@ void SDNode::dump(const SelectionDAG *G) const {
       break;
     }
     if (doExt)
-      std::cerr << MVT::getValueTypeString(LD->getLoadVT()) << ">";
+      std::cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">";
 
     if (LD->getAddressingMode() == ISD::PRE_INDEXED)
       std::cerr << " <pre>";
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 75c0cb337e7..486f054ad02 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -145,7 +145,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
       break;
     }
     if (doExt)
-      Op = Op + MVT::getValueTypeString(LD->getLoadVT()) + ">";
+      Op = Op + MVT::getValueTypeString(LD->getLoadedVT()) + ">";
 
     if (LD->getAddressingMode() == ISD::PRE_INDEXED)
       Op = Op + "<pre>";
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 73cefc4e385..0183678464f 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -555,7 +555,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
   case ISD::LOAD: {
     if (ISD::isZEXTLoad(Op.Val)) {
       LoadSDNode *LD = cast<LoadSDNode>(Op);
-      MVT::ValueType VT = LD->getLoadVT();
+      MVT::ValueType VT = LD->getLoadedVT();
       KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
     }
     break;
@@ -896,7 +896,7 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
   case ISD::LOAD: {
     if (ISD::isZEXTLoad(Op.Val)) {
       LoadSDNode *LD = cast<LoadSDNode>(Op);
-      MVT::ValueType VT = LD->getLoadVT();
+      MVT::ValueType VT = LD->getLoadedVT();
       KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
     }
     return;
@@ -1205,10 +1205,10 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
     switch (ExtType) {
     default: break;
     case ISD::SEXTLOAD:    // '17' bits known
-      Tmp = MVT::getSizeInBits(LD->getLoadVT());
+      Tmp = MVT::getSizeInBits(LD->getLoadedVT());
       return VTBits-Tmp+1;
     case ISD::ZEXTLOAD:    // '16' bits known
-      Tmp = MVT::getSizeInBits(LD->getLoadVT());
+      Tmp = MVT::getSizeInBits(LD->getLoadedVT());
       return VTBits-Tmp;
     }
   }
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 79252bcbaef..f4b60afdfbf 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -460,7 +460,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
     AddToISelQueue(Chain);
     AddToISelQueue(Address);
 
-    MVT::ValueType TypeBeingLoaded = LD->getLoadVT();
+    MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
     unsigned Opc;
     switch (TypeBeingLoaded) {
     default:
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 6e9a695a93d..bd2b2e576c1 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -411,69 +411,69 @@ def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
 // extending load & truncstore fragments.
 def extloadi1  : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i1;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
   return false;
 }]>;
 def extloadi8  : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i8;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i8;
   return false;
 }]>;
 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i16;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i16;
   return false;
 }]>;
 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i32;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i32;
   return false;
 }]>;
 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::f32;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::f32;
   return false;
 }]>;
 
 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isSEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i1;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
   return false;
 }]>;
 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isSEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i8;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i8;
   return false;
 }]>;
 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isSEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i16;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i16;
   return false;
 }]>;
 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isSEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i32;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i32;
   return false;
 }]>;
 
 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isZEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i1;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
   return false;
 }]>;
 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isZEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i8;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i8;
   return false;
 }]>;
 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isZEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i16;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i16;
   return false;
 }]>;
 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
   if (ISD::isZEXTLoad(N))
-    return cast<LoadSDNode>(N)->getLoadVT() == MVT::i32;
+    return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i32;
   return false;
 }]>;