From: Greg Meiste Date: Wed, 8 Sep 2010 18:45:06 +0000 (-0500) Subject: [ARM] tegra: stingray: Fix CPU DVFS X-Git-Tag: firefly_0821_release~9834^2~575 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2e760aa5ab26ad56b882a210cb6dbe5f2c301694;p=firefly-linux-kernel-4.4.55.git [ARM] tegra: stingray: Fix CPU DVFS P0 and later models were changed to put the cpu_vdd regulator in MODE 1, rather than the previous MODE 3 value. This caused DVFS to appear to work but actually have no impact on the cpu voltage. In addition, when resuming from LP0, the CPU voltage must be 1.0v. To guarantee this, the voltage needs to be set upon entering suspend, so when the regulator is re-enabled, it is the correct voltage before code begins executing. Change-Id: I3580c832dbb4b5ce9ce7bd0089352a72b3b3869c Signed-off-by: Greg Meiste --- diff --git a/arch/arm/mach-tegra/board-stingray-power.c b/arch/arm/mach-tegra/board-stingray-power.c index 3f97f7435a79..9ba3518b87ad 100644 --- a/arch/arm/mach-tegra/board-stingray-power.c +++ b/arch/arm/mach-tegra/board-stingray-power.c @@ -660,6 +660,11 @@ struct regulator_init_data max8649_regulator_init_data[] = { .max_uV = 1100000, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, .always_on = 1, + .state_mem = { + .uV = 1000000, + .enabled = 1, + .disabled = 0, + } }, .num_consumer_supplies = ARRAY_SIZE(max8649_consumers), .consumer_supplies = max8649_consumers, @@ -668,7 +673,7 @@ struct regulator_init_data max8649_regulator_init_data[] = { struct max8649_platform_data stingray_max8649_pdata = { .regulator = max8649_regulator_init_data, - .mode = 3, + .mode = 1, .extclk = 0, .ramp_timing = MAX8649_RAMP_32MV, .ramp_down = 0, @@ -727,6 +732,8 @@ int __init stingray_power_init(void) stingray_display_led.led_regulator = "sw5"; stingray_display_led.cpcap_register = CPCAP_REG_KLC, stingray_privacy_led.led_regulator = "sw5"; + + stingray_max8649_pdata.mode = 3; } tegra_gpio_enable(TEGRA_GPIO_PT2);