From: Wu Liang feng Date: Thu, 24 Mar 2016 07:38:02 +0000 (+0800) Subject: usb: dwc3: make usb2 phy interface configurable in DT X-Git-Tag: firefly_0821_release~3017 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2ef6df639e07b312f9cde351ba4a5d28c0009a82;p=firefly-linux-kernel-4.4.55.git usb: dwc3: make usb2 phy interface configurable in DT Add snps,phyif_utmi_16_bits devicetree property. USB2 phy interface is hardware property, and it's platform dependent, so we need to configure it in devicetree to set the core to support a UTMI+ PHY with an 8- or 16-bit interface. And according to dwc3 databook, the GUSB2PHYCFG.USBTRDTIM must set to the required values for the usb2 phy interface. Change-Id: If1c636edc6be3c9a79b4b0b89737a925d8dd3abe Signed-off-by: Wu Liang feng --- diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index c005ada1fa81..f1806c4f21e8 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -20,6 +20,8 @@ Optional properties: Only really useful for FPGA builds. - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled - snps,lpm-nyet-threshold: LPM NYET threshold + - snps,phyif_utmi_16_bits: true when configure the core to support + UTMI+ PHY with an 16-bit interface. - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk - snps,req_p1p2p3_quirk: when set, the core will always request for diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 47f3ab7e45a5..e7aab0926712 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -430,6 +430,7 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) static int dwc3_phy_setup(struct dwc3 *dwc) { u32 reg; + u32 usbtrdtim; int ret; reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); @@ -522,6 +523,15 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u2_freeclk_exists_quirk) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + if (dwc->phyif_utmi_16_bits) + reg |= DWC3_GUSB2PHYCFG_PHYIF; + + usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ? + USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT; + + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); return 0; @@ -939,6 +949,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,dis_enblslpm_quirk"); dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, "snps,dis_u2_freeclk_exists_quirk"); + dwc->phyif_utmi_16_bits = device_property_read_bool(dev, + "snps,phyif_utmi_16_bits"); dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); @@ -975,6 +987,7 @@ static int dwc3_probe(struct platform_device *pdev) dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk; dwc->dis_u2_freeclk_exists_quirk = pdata->dis_u2_freeclk_exists_quirk; + dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits; dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; if (pdata->tx_de_emphasis) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 8e57ea6148ec..4e0a319da9da 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -181,7 +181,12 @@ #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) +#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USBTRDTIM_UTMI_8_BIT 9 +#define USBTRDTIM_UTMI_16_BIT 5 /* Global USB2 PHY Vendor Control Register */ #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) @@ -714,6 +719,8 @@ struct dwc3_scratchpad_array { * @start_config_issued: true when StartConfig command has been issued * @three_stage_setup: set if we perform a three phase setup * @usb3_lpm_capable: set if hadrware supports Link Power Management + * @phyif_utmi_16_bits: set if configure the core to support UTMI+ PHY + * with an 16-bit interface * @disable_scramble_quirk: set if we enable the disable scramble quirk * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk @@ -862,6 +869,7 @@ struct dwc3 { unsigned setup_packet_pending:1; unsigned three_stage_setup:1; unsigned usb3_lpm_capable:1; + unsigned phyif_utmi_16_bits:1; unsigned disable_scramble_quirk:1; unsigned u2exit_lfps_quirk:1; diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index 5e1209817ce0..aa5739a58c86 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -25,6 +25,7 @@ struct dwc3_platform_data { enum usb_dr_mode dr_mode; bool tx_fifo_resize; bool usb3_lpm_capable; + bool phyif_utmi_16_bits; unsigned is_utmi_l1_suspend:1; u8 hird_threshold;