From: S. Holmes <sholmes@nvidia.com>
Date: Thu, 19 Aug 2010 15:31:17 +0000 (-0600)
Subject: tegra: nvrm: Add VDE, VCP, and BSEA to RM clock & module APIs
X-Git-Tag: firefly_0821_release~9834^2~681
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2fa2329a6fc8e70ffe845f22e46b3b8d1fbed83a;p=firefly-linux-kernel-4.4.55.git

tegra: nvrm: Add VDE, VCP, and BSEA to RM clock & module APIs

Add the VDE, VCP, and BSEA blocks to the RM clock and module APIs so that
video and audio playback will work.

Change-Id: I4a7d9121239967f6b76b0a585a818d1047a56993
---

diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c
index 5bf58eaebd8b..a38683081ac4 100644
--- a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c
@@ -145,6 +145,21 @@ void NvRmModuleGetBaseAddress( NvRmDeviceHandle hRmDeviceHandle, NvRmModuleID Mo
 		*pSize = 256 * 1024;
 		break;
 
+	case NvRmModuleID_Vcp:
+		*pBaseAddress = 0x6000e000;
+		*pSize = 4096;
+		break;
+
+    case NvRmModuleID_BseA:
+        *pBaseAddress = 0x60011000;
+        *pSize = 4096;
+        break;
+
+    case NvRmModuleID_Vde:
+        *pBaseAddress = 0x6001a000;
+        *pSize = 0x3c00;
+        break;
+
 	case NvRmModuleID_Vi:
 		*pBaseAddress = 0x54080000;
 		*pSize = 256 * 1024;
@@ -167,6 +182,9 @@ void NvRmModuleGetBaseAddress( NvRmDeviceHandle hRmDeviceHandle, NvRmModuleID Mo
 #define is_csi(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Csi)
 #define is_isp(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Isp)
 #define is_vi(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vi)
+#define is_vcp(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vcp)
+#define is_bsea(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_BseA)
+#define is_vde(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vde)
 
 void NvRmModuleReset(NvRmDeviceHandle hRmDevice, NvRmModuleID Module)
 {
@@ -183,6 +201,12 @@ void NvRmModuleReset(NvRmDeviceHandle hRmDevice, NvRmModuleID Module)
         clk = clk_get_sys("vi", NULL);
     else if (is_isp(Module))
         clk = clk_get_sys("isp", NULL);
+    else if (is_vcp(Module))
+        clk = clk_get_sys("vcp", NULL);
+    else if (is_bsea(Module))
+        clk = clk_get_sys("bsea", NULL);
+    else if (is_vde(Module))
+        clk = clk_get_sys("vde", NULL);
     else {
         printk("%s MOD[%lu] INST[%lu] not implemented\n", __func__,
                NVRM_MODULE_ID_MODULE(Module),
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c
index a644842ce6c6..c9bf02999034 100644
--- a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c
@@ -48,6 +48,12 @@
 
 #define is_isp(module) (NVRM_MODULE_ID_MODULE(module)==NvRmModuleID_Isp)
 
+#define is_vcp(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vcp)
+
+#define is_bsea(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_BseA)
+
+#define is_vde(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vde)
+
 #define CLK_VI_CORE_EXTERNAL (1<<24)
 #define CLK_VI_PAD_INTERNAL (1<<25)
 
@@ -138,6 +144,9 @@ NvError NvRmPowerModuleClockControl(
     const char *vi_names[] = { "vi", "vi_sensor", "csus", NULL };
     const char *csi_names[] = { "csi", NULL };
     const char *isp_names[] = { "isp", NULL };
+    const char *vcp_names[] = { "vcp", NULL };
+    const char *bsea_names[] = { "bsea", NULL };
+    const char *vde_names[] = { "vde", NULL };
     const char **names = NULL;
 
     if (is_vi(ModuleId))
@@ -146,12 +155,18 @@ NvError NvRmPowerModuleClockControl(
         names = csi_names;
     else if (is_isp(ModuleId))
         names = isp_names;
+    else if (is_vcp(ModuleId))
+        names = vcp_names;
+    else if (is_bsea(ModuleId))
+        names = bsea_names;
+    else if (is_vde(ModuleId))
+        names = vde_names;
 
     if (!names) {
         pr_err("%s: MOD[%lu] INST[%lu] not supported\n", __func__,
                NVRM_MODULE_ID_MODULE(ModuleId),
                NVRM_MODULE_ID_INSTANCE(ModuleId));
-        return NvSuccess;
+        return NvError_BadParameter;
     }
 
     for ( ; *names ; names++) {
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 5e32c0efb87f..cceef8916487 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1795,6 +1795,8 @@ struct clk tegra_periph_clks[] = {
 	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
 	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
 	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("vcp",	"vcp",			NULL,	29,	0,	250000000, mux_clk_m, 			0),
+	PERIPH_CLK("bsea",	"bsea",			NULL,	62,	0,	250000000, mux_clk_m, 			0),
 	PERIPH_CLK("vde",	"vde",			NULL,	61,	0x1c8,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
 	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
 	/* FIXME: what is la? */