From: Bob Wilson <bob.wilson@apple.com>
Date: Mon, 29 Nov 2010 19:35:23 +0000 (+0000)
Subject: Fix copy-and-paste errors in VLD2-dup scheduling itineraries.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=2fcda63763ef010c57f6e7f250868e355075f6cf;p=oota-llvm.git

Fix copy-and-paste errors in VLD2-dup scheduling itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120311 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td
index a364c4eccb1..be92562a2e5 100644
--- a/lib/Target/ARM/ARMScheduleA8.td
+++ b/lib/Target/ARM/ARMScheduleA8.td
@@ -527,13 +527,13 @@ def CortexA8Itineraries : ProcessorItineraries<
   InstrItinData<IIC_VLD2dup,  [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                InstrStage<2, [A8_NLSPipe], 0>,
                                InstrStage<2, [A8_LSPipe]>],
-                              [2, 1]>,
+                              [2, 2, 1]>,
   //
   // VLD2dupu
   InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                InstrStage<2, [A8_NLSPipe], 0>,
                                InstrStage<2, [A8_LSPipe]>],
-                              [2, 2, 1, 1]>,
+                              [2, 2, 2, 1, 1]>,
   //
   // VLD3
   InstrItinData<IIC_VLD3,     [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index 53c53bf1af8..d775a9f26fe 100644
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -894,7 +894,7 @@ def CortexA9Itineraries : ProcessorItineraries<
                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
                                InstrStage<2, [A9_NPipe], 0>,
                                InstrStage<2, [A9_LSUnit]>],
-                              [3, 1]>,
+                              [3, 3, 1]>,
   //
   // VLD2dupu
   InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
@@ -903,7 +903,7 @@ def CortexA9Itineraries : ProcessorItineraries<
                                InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
                                InstrStage<2, [A9_NPipe], 0>,
                                InstrStage<2, [A9_LSUnit]>],
-                              [3, 2, 1, 1]>,
+                              [3, 3, 2, 1, 1]>,
   //
   // VLD3
   InstrItinData<IIC_VLD3,     [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,