From: Zheng Yang <zhengyang@rock-chips.com>
Date: Mon, 27 Mar 2017 01:38:26 +0000 (+0800)
Subject: drm: bridge: dw-hdmi-i2s-audio: enable INSERT_PCUV bit for LPCM
X-Git-Tag: firefly_0821_release~206
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=30347643504ef511b4858a381416e60f47f13d7e;p=firefly-linux-kernel-4.4.55.git

drm: bridge: dw-hdmi-i2s-audio: enable INSERT_PCUV bit for LPCM

dw-hdmi introduced insert_pcuv bit in version 2.10a. When
set (1'b1), this bit enables the insertion of the PCUV
(Parity, Channel Status, User bit and Validity) bits on the
incoming audio stream (support limited to Linear PCM audio).

Change-Id: Ib12a50bf7064ac78dbf143f1ea35d7f68f861877
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
---

diff --git a/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c
index 74ae2c25b4e5..84c2a316aac3 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c
@@ -85,7 +85,14 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
 	hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS);
 	hdmi_write(audio, conf0, HDMI_AUD_CONF0);
 	hdmi_write(audio, conf1, HDMI_AUD_CONF1);
-
+	/*
+	 * dw-hdmi introduced insert_pcuv bit in version 2.10a.
+	 * When set (1'b1), this bit enables the insertion of the PCUV
+	 * (Parity, Channel Status, User bit and Validity) bits on the
+	 * incoming audio stream (support limited to Linear PCM audio)
+	 */
+	if (hdmi_read(audio, HDMI_DESIGN_ID) > 0x21)
+		hdmi_write(audio, HDMI_AUD_CONF2_INSERT_PCUV, HDMI_AUD_CONF2);
 	dw_hdmi_audio_enable(hdmi);
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/dw-hdmi.h
index dbc717306a32..36859b35ef8f 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/dw-hdmi.h
@@ -915,6 +915,11 @@ enum {
 	HDMI_AUD_CONF1_WIDTH_16 = 0x10,
 	HDMI_AUD_CONF1_WIDTH_24 = 0x18,
 
+/* AUD_CONF2 filed values */
+	HDMI_AUD_CONF2_HBR = 0x1,
+	HDMI_AUD_CONF2_NLPCM = 0x2,
+	HDMI_AUD_CONF2_INSERT_PCUV = 0x04,
+
 /* AUD_CTS3 field values */
 	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
 	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,