From: 黄涛 Date: Wed, 17 Jul 2013 11:03:37 +0000 (+0800) Subject: rk2928: gpio.h add RK30 define X-Git-Tag: firefly_0821_release~6884 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=30af6f70b96c4a007bc344a23c1900a09482e663;p=firefly-linux-kernel-4.4.55.git rk2928: gpio.h add RK30 define --- diff --git a/arch/arm/mach-rk2928/include/mach/gpio.h b/arch/arm/mach-rk2928/include/mach/gpio.h index 4043d1a484ea..9573dc13ad82 100755 --- a/arch/arm/mach-rk2928/include/mach/gpio.h +++ b/arch/arm/mach-rk2928/include/mach/gpio.h @@ -138,6 +138,138 @@ #define RK2928_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30) #define RK2928_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31) +#define RK30_PIN0_PA0 RK2928_PIN0_PA0 +#define RK30_PIN0_PA1 RK2928_PIN0_PA1 +#define RK30_PIN0_PA2 RK2928_PIN0_PA2 +#define RK30_PIN0_PA3 RK2928_PIN0_PA3 +#define RK30_PIN0_PA4 RK2928_PIN0_PA4 +#define RK30_PIN0_PA5 RK2928_PIN0_PA5 +#define RK30_PIN0_PA6 RK2928_PIN0_PA6 +#define RK30_PIN0_PA7 RK2928_PIN0_PA7 +#define RK30_PIN0_PB0 RK2928_PIN0_PB0 +#define RK30_PIN0_PB1 RK2928_PIN0_PB1 +#define RK30_PIN0_PB2 RK2928_PIN0_PB2 +#define RK30_PIN0_PB3 RK2928_PIN0_PB3 +#define RK30_PIN0_PB4 RK2928_PIN0_PB4 +#define RK30_PIN0_PB5 RK2928_PIN0_PB5 +#define RK30_PIN0_PB6 RK2928_PIN0_PB6 +#define RK30_PIN0_PB7 RK2928_PIN0_PB7 +#define RK30_PIN0_PC0 RK2928_PIN0_PC0 +#define RK30_PIN0_PC1 RK2928_PIN0_PC1 +#define RK30_PIN0_PC2 RK2928_PIN0_PC2 +#define RK30_PIN0_PC3 RK2928_PIN0_PC3 +#define RK30_PIN0_PC4 RK2928_PIN0_PC4 +#define RK30_PIN0_PC5 RK2928_PIN0_PC5 +#define RK30_PIN0_PC6 RK2928_PIN0_PC6 +#define RK30_PIN0_PC7 RK2928_PIN0_PC7 +#define RK30_PIN0_PD0 RK2928_PIN0_PD0 +#define RK30_PIN0_PD1 RK2928_PIN0_PD1 +#define RK30_PIN0_PD2 RK2928_PIN0_PD2 +#define RK30_PIN0_PD3 RK2928_PIN0_PD3 +#define RK30_PIN0_PD4 RK2928_PIN0_PD4 +#define RK30_PIN0_PD5 RK2928_PIN0_PD5 +#define RK30_PIN0_PD6 RK2928_PIN0_PD6 +#define RK30_PIN0_PD7 RK2928_PIN0_PD7 + +#define RK30_PIN1_PA0 RK2928_PIN1_PA0 +#define RK30_PIN1_PA1 RK2928_PIN1_PA1 +#define RK30_PIN1_PA2 RK2928_PIN1_PA2 +#define RK30_PIN1_PA3 RK2928_PIN1_PA3 +#define RK30_PIN1_PA4 RK2928_PIN1_PA4 +#define RK30_PIN1_PA5 RK2928_PIN1_PA5 +#define RK30_PIN1_PA6 RK2928_PIN1_PA6 +#define RK30_PIN1_PA7 RK2928_PIN1_PA7 +#define RK30_PIN1_PB0 RK2928_PIN1_PB0 +#define RK30_PIN1_PB1 RK2928_PIN1_PB1 +#define RK30_PIN1_PB2 RK2928_PIN1_PB2 +#define RK30_PIN1_PB3 RK2928_PIN1_PB3 +#define RK30_PIN1_PB4 RK2928_PIN1_PB4 +#define RK30_PIN1_PB5 RK2928_PIN1_PB5 +#define RK30_PIN1_PB6 RK2928_PIN1_PB6 +#define RK30_PIN1_PB7 RK2928_PIN1_PB7 +#define RK30_PIN1_PC0 RK2928_PIN1_PC0 +#define RK30_PIN1_PC1 RK2928_PIN1_PC1 +#define RK30_PIN1_PC2 RK2928_PIN1_PC2 +#define RK30_PIN1_PC3 RK2928_PIN1_PC3 +#define RK30_PIN1_PC4 RK2928_PIN1_PC4 +#define RK30_PIN1_PC5 RK2928_PIN1_PC5 +#define RK30_PIN1_PC6 RK2928_PIN1_PC6 +#define RK30_PIN1_PC7 RK2928_PIN1_PC7 +#define RK30_PIN1_PD0 RK2928_PIN1_PD0 +#define RK30_PIN1_PD1 RK2928_PIN1_PD1 +#define RK30_PIN1_PD2 RK2928_PIN1_PD2 +#define RK30_PIN1_PD3 RK2928_PIN1_PD3 +#define RK30_PIN1_PD4 RK2928_PIN1_PD4 +#define RK30_PIN1_PD5 RK2928_PIN1_PD5 +#define RK30_PIN1_PD6 RK2928_PIN1_PD6 +#define RK30_PIN1_PD7 RK2928_PIN1_PD7 + +#define RK30_PIN2_PA0 RK2928_PIN2_PA0 +#define RK30_PIN2_PA1 RK2928_PIN2_PA1 +#define RK30_PIN2_PA2 RK2928_PIN2_PA2 +#define RK30_PIN2_PA3 RK2928_PIN2_PA3 +#define RK30_PIN2_PA4 RK2928_PIN2_PA4 +#define RK30_PIN2_PA5 RK2928_PIN2_PA5 +#define RK30_PIN2_PA6 RK2928_PIN2_PA6 +#define RK30_PIN2_PA7 RK2928_PIN2_PA7 +#define RK30_PIN2_PB0 RK2928_PIN2_PB0 +#define RK30_PIN2_PB1 RK2928_PIN2_PB1 +#define RK30_PIN2_PB2 RK2928_PIN2_PB2 +#define RK30_PIN2_PB3 RK2928_PIN2_PB3 +#define RK30_PIN2_PB4 RK2928_PIN2_PB4 +#define RK30_PIN2_PB5 RK2928_PIN2_PB5 +#define RK30_PIN2_PB6 RK2928_PIN2_PB6 +#define RK30_PIN2_PB7 RK2928_PIN2_PB7 +#define RK30_PIN2_PC0 RK2928_PIN2_PC0 +#define RK30_PIN2_PC1 RK2928_PIN2_PC1 +#define RK30_PIN2_PC2 RK2928_PIN2_PC2 +#define RK30_PIN2_PC3 RK2928_PIN2_PC3 +#define RK30_PIN2_PC4 RK2928_PIN2_PC4 +#define RK30_PIN2_PC5 RK2928_PIN2_PC5 +#define RK30_PIN2_PC6 RK2928_PIN2_PC6 +#define RK30_PIN2_PC7 RK2928_PIN2_PC7 +#define RK30_PIN2_PD0 RK2928_PIN2_PD0 +#define RK30_PIN2_PD1 RK2928_PIN2_PD1 +#define RK30_PIN2_PD2 RK2928_PIN2_PD2 +#define RK30_PIN2_PD3 RK2928_PIN2_PD3 +#define RK30_PIN2_PD4 RK2928_PIN2_PD4 +#define RK30_PIN2_PD5 RK2928_PIN2_PD5 +#define RK30_PIN2_PD6 RK2928_PIN2_PD6 +#define RK30_PIN2_PD7 RK2928_PIN2_PD7 + +#define RK30_PIN3_PA0 RK2928_PIN3_PA0 +#define RK30_PIN3_PA1 RK2928_PIN3_PA1 +#define RK30_PIN3_PA2 RK2928_PIN3_PA2 +#define RK30_PIN3_PA3 RK2928_PIN3_PA3 +#define RK30_PIN3_PA4 RK2928_PIN3_PA4 +#define RK30_PIN3_PA5 RK2928_PIN3_PA5 +#define RK30_PIN3_PA6 RK2928_PIN3_PA6 +#define RK30_PIN3_PA7 RK2928_PIN3_PA7 +#define RK30_PIN3_PB0 RK2928_PIN3_PB0 +#define RK30_PIN3_PB1 RK2928_PIN3_PB1 +#define RK30_PIN3_PB2 RK2928_PIN3_PB2 +#define RK30_PIN3_PB3 RK2928_PIN3_PB3 +#define RK30_PIN3_PB4 RK2928_PIN3_PB4 +#define RK30_PIN3_PB5 RK2928_PIN3_PB5 +#define RK30_PIN3_PB6 RK2928_PIN3_PB6 +#define RK30_PIN3_PB7 RK2928_PIN3_PB7 +#define RK30_PIN3_PC0 RK2928_PIN3_PC0 +#define RK30_PIN3_PC1 RK2928_PIN3_PC1 +#define RK30_PIN3_PC2 RK2928_PIN3_PC2 +#define RK30_PIN3_PC3 RK2928_PIN3_PC3 +#define RK30_PIN3_PC4 RK2928_PIN3_PC4 +#define RK30_PIN3_PC5 RK2928_PIN3_PC5 +#define RK30_PIN3_PC6 RK2928_PIN3_PC6 +#define RK30_PIN3_PC7 RK2928_PIN3_PC7 +#define RK30_PIN3_PD0 RK2928_PIN3_PD0 +#define RK30_PIN3_PD1 RK2928_PIN3_PD1 +#define RK30_PIN3_PD2 RK2928_PIN3_PD2 +#define RK30_PIN3_PD3 RK2928_PIN3_PD3 +#define RK30_PIN3_PD4 RK2928_PIN3_PD4 +#define RK30_PIN3_PD5 RK2928_PIN3_PD5 +#define RK30_PIN3_PD6 RK2928_PIN3_PD6 +#define RK30_PIN3_PD7 RK2928_PIN3_PD7 + #include #endif