From: Evgeniy Stepanov <eugeni.stepanov@gmail.com>
Date: Tue, 25 Aug 2015 20:59:26 +0000 (+0000)
Subject: Use CHECK-LABEL in MSan IR tests.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3104975f8a902e5dd3e82927403d0e54f3688615;p=oota-llvm.git

Use CHECK-LABEL in MSan IR tests.

This actually found one case when a test was matching instructions
from the output of a different test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245974 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Instrumentation/MemorySanitizer/atomics.ll b/test/Instrumentation/MemorySanitizer/atomics.ll
index e896eaebdd3..8033ed1e2d4 100644
--- a/test/Instrumentation/MemorySanitizer/atomics.ll
+++ b/test/Instrumentation/MemorySanitizer/atomics.ll
@@ -13,7 +13,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @AtomicRmwXchg
+; CHECK-LABEL: @AtomicRmwXchg
 ; CHECK: store i32 0,
 ; CHECK: atomicrmw xchg {{.*}} seq_cst
 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls
@@ -28,7 +28,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @AtomicRmwMax
+; CHECK-LABEL: @AtomicRmwMax
 ; CHECK: store i32 0,
 ; CHECK: atomicrmw max {{.*}} seq_cst
 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls
@@ -44,7 +44,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @Cmpxchg
+; CHECK-LABEL: @Cmpxchg
 ; CHECK: store { i32, i1 } zeroinitializer,
 ; CHECK: icmp
 ; CHECK: br
@@ -63,7 +63,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @CmpxchgMonotonic
+; CHECK-LABEL: @CmpxchgMonotonic
 ; CHECK: store { i32, i1 } zeroinitializer,
 ; CHECK: icmp
 ; CHECK: br
@@ -81,7 +81,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @AtomicLoad
+; CHECK-LABEL: @AtomicLoad
 ; CHECK: load atomic i32, i32* {{.*}} seq_cst, align 16
 ; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
@@ -96,7 +96,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @AtomicLoadAcquire
+; CHECK-LABEL: @AtomicLoadAcquire
 ; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
 ; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
@@ -111,7 +111,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @AtomicLoadMonotonic
+; CHECK-LABEL: @AtomicLoadMonotonic
 ; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
 ; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
@@ -126,7 +126,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @AtomicLoadUnordered
+; CHECK-LABEL: @AtomicLoadUnordered
 ; CHECK: load atomic i32, i32* {{.*}} acquire, align 16
 ; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16
 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls
@@ -141,7 +141,7 @@ entry:
   ret void
 }
 
-; CHECK: @AtomicStore
+; CHECK-LABEL: @AtomicStore
 ; CHECK-NOT: @__msan_param_tls
 ; CHECK: store i32 0, i32* {{.*}}, align 16
 ; CHECK: store atomic i32 %x, i32* %p seq_cst, align 16
@@ -156,7 +156,7 @@ entry:
   ret void
 }
 
-; CHECK: @AtomicStoreRelease
+; CHECK-LABEL: @AtomicStoreRelease
 ; CHECK-NOT: @__msan_param_tls
 ; CHECK: store i32 0, i32* {{.*}}, align 16
 ; CHECK: store atomic i32 %x, i32* %p release, align 16
@@ -171,7 +171,7 @@ entry:
   ret void
 }
 
-; CHECK: @AtomicStoreMonotonic
+; CHECK-LABEL: @AtomicStoreMonotonic
 ; CHECK-NOT: @__msan_param_tls
 ; CHECK: store i32 0, i32* {{.*}}, align 16
 ; CHECK: store atomic i32 %x, i32* %p release, align 16
@@ -186,7 +186,7 @@ entry:
   ret void
 }
 
-; CHECK: @AtomicStoreUnordered
+; CHECK-LABEL: @AtomicStoreUnordered
 ; CHECK-NOT: @__msan_param_tls
 ; CHECK: store i32 0, i32* {{.*}}, align 16
 ; CHECK: store atomic i32 %x, i32* %p release, align 16
diff --git a/test/Instrumentation/MemorySanitizer/check_access_address.ll b/test/Instrumentation/MemorySanitizer/check_access_address.ll
index 5e1a3f4442f..723d6f0cd34 100644
--- a/test/Instrumentation/MemorySanitizer/check_access_address.ll
+++ b/test/Instrumentation/MemorySanitizer/check_access_address.ll
@@ -12,7 +12,7 @@ entry:
   ret <2 x i64> %x
 }
 
-; CHECK: @ByValArgumentShadowLargeAlignment
+; CHECK-LABEL: @ByValArgumentShadowLargeAlignment
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 16, i32 8, i1 false)
 ; CHECK: ret <2 x i64>
 
@@ -23,6 +23,6 @@ entry:
   ret i16 %x
 }
 
-; CHECK: @ByValArgumentShadowSmallAlignment
+; CHECK-LABEL: @ByValArgumentShadowSmallAlignment
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 2, i32 2, i1 false)
 ; CHECK: ret i16
diff --git a/test/Instrumentation/MemorySanitizer/msan_basic.ll b/test/Instrumentation/MemorySanitizer/msan_basic.ll
index 73e2c7ac120..6ae7c1d4427 100644
--- a/test/Instrumentation/MemorySanitizer/msan_basic.ll
+++ b/test/Instrumentation/MemorySanitizer/msan_basic.ll
@@ -28,7 +28,7 @@ entry:
   ret void
 }
 
-; CHECK: @Store
+; CHECK-LABEL: @Store
 ; CHECK: load {{.*}} @__msan_param_tls
 ; CHECK-ORIGINS: load {{.*}} @__msan_param_origin_tls
 ; CHECK: store
@@ -52,7 +52,7 @@ entry:
   ret void
 }
 
-; CHECK: @AlignedStore
+; CHECK-LABEL: @AlignedStore
 ; CHECK: load {{.*}} @__msan_param_tls
 ; CHECK-ORIGINS: load {{.*}} @__msan_param_origin_tls
 ; CHECK: store {{.*}} align 32
@@ -83,7 +83,7 @@ if.end:                                           ; preds = %entry, %if.then
 
 declare void @foo(...)
 
-; CHECK: @LoadAndCmp
+; CHECK-LABEL: @LoadAndCmp
 ; CHECK: = load
 ; CHECK: = load
 ; CHECK: call void @__msan_warning_noreturn()
@@ -97,7 +97,7 @@ entry:
   ret i32 123
 }
 
-; CHECK: @ReturnInt
+; CHECK-LABEL: @ReturnInt
 ; CHECK: store i32 0,{{.*}}__msan_retval_tls
 ; CHECK: ret i32
 
@@ -109,7 +109,7 @@ entry:
   ret void
 }
 
-; CHECK: @CopyRetVal
+; CHECK-LABEL: @CopyRetVal
 ; CHECK: load{{.*}}__msan_retval_tls
 ; CHECK: store
 ; CHECK: store
@@ -136,7 +136,7 @@ entry:
   ret void
 }
 
-; CHECK: @FuncWithPhi
+; CHECK-LABEL: @FuncWithPhi
 ; CHECK: = phi
 ; CHECK-NEXT: = phi
 ; CHECK: store
@@ -152,7 +152,7 @@ entry:
   ret void
 }
 
-; CHECK: @ShlConst
+; CHECK-LABEL: @ShlConst
 ; CHECK: = load
 ; CHECK: = load
 ; CHECK: shl
@@ -170,7 +170,7 @@ entry:
   ret void
 }
 
-; CHECK: @ShlNonConst
+; CHECK-LABEL: @ShlNonConst
 ; CHECK: = load
 ; CHECK: = load
 ; CHECK: = sext i1
@@ -187,7 +187,7 @@ entry:
   ret void
 }
 
-; CHECK: @SExt
+; CHECK-LABEL: @SExt
 ; CHECK: = load
 ; CHECK: = load
 ; CHECK: = sext
@@ -206,7 +206,7 @@ entry:
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 
-; CHECK: @MemSet
+; CHECK-LABEL: @MemSet
 ; CHECK: call i8* @__msan_memset
 ; CHECK: ret void
 
@@ -220,7 +220,7 @@ entry:
 
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
 
-; CHECK: @MemCpy
+; CHECK-LABEL: @MemCpy
 ; CHECK: call i8* @__msan_memcpy
 ; CHECK: ret void
 
@@ -234,7 +234,7 @@ entry:
 
 declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
 
-; CHECK: @MemMove
+; CHECK-LABEL: @MemMove
 ; CHECK: call i8* @__msan_memmove
 ; CHECK: ret void
 
@@ -247,7 +247,7 @@ entry:
   ret i32 %cond
 }
 
-; CHECK: @Select
+; CHECK-LABEL: @Select
 ; CHECK: select i1
 ; CHECK-DAG: or i32
 ; CHECK-DAG: xor i32
@@ -271,7 +271,7 @@ entry:
   ret <8 x i16> %cond
 }
 
-; CHECK: @SelectVector
+; CHECK-LABEL: @SelectVector
 ; CHECK: select <8 x i1>
 ; CHECK-DAG: or <8 x i16>
 ; CHECK-DAG: xor <8 x i16>
@@ -295,7 +295,7 @@ entry:
   ret <8 x i16> %cond
 }
 
-; CHECK: @SelectVector2
+; CHECK-LABEL: @SelectVector2
 ; CHECK: select i1
 ; CHECK-DAG: or <8 x i16>
 ; CHECK-DAG: xor <8 x i16>
@@ -313,7 +313,7 @@ entry:
   ret { i64, i64 } %c
 }
 
-; CHECK: @SelectStruct
+; CHECK-LABEL: @SelectStruct
 ; CHECK: select i1 {{.*}}, { i64, i64 }
 ; CHECK-NEXT: select i1 {{.*}}, { i64, i64 } { i64 -1, i64 -1 }, { i64, i64 }
 ; CHECK-ORIGINS: select i1
@@ -328,7 +328,7 @@ entry:
   ret { i64*, double } %c
 }
 
-; CHECK: @SelectStruct2
+; CHECK-LABEL: @SelectStruct2
 ; CHECK: select i1 {{.*}}, { i64, i64 }
 ; CHECK-NEXT: select i1 {{.*}}, { i64, i64 } { i64 -1, i64 -1 }, { i64, i64 }
 ; CHECK-ORIGINS: select i1
@@ -343,7 +343,7 @@ entry:
   ret i8* %0
 }
 
-; CHECK: @IntToPtr
+; CHECK-LABEL: @IntToPtr
 ; CHECK: load i64, i64*{{.*}}__msan_param_tls
 ; CHECK-ORIGINS-NEXT: load i32, i32*{{.*}}__msan_param_origin_tls
 ; CHECK-NEXT: inttoptr
@@ -357,7 +357,7 @@ entry:
   ret i8* %0
 }
 
-; CHECK: @IntToPtr_ZExt
+; CHECK-LABEL: @IntToPtr_ZExt
 ; CHECK: load i16, i16*{{.*}}__msan_param_tls
 ; CHECK: zext
 ; CHECK-NEXT: inttoptr
@@ -374,7 +374,7 @@ entry:
   ret i32 %div
 }
 
-; CHECK: @Div
+; CHECK-LABEL: @Div
 ; CHECK: icmp
 ; CHECK: call void @__msan_warning
 ; CHECK-NOT: icmp
@@ -390,7 +390,7 @@ define zeroext i1 @ICmpSLT(i32 %x) nounwind uwtable readnone sanitize_memory {
   ret i1 %1
 }
 
-; CHECK: @ICmpSLT
+; CHECK-LABEL: @ICmpSLT
 ; CHECK: icmp slt
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: icmp slt
@@ -402,7 +402,7 @@ define zeroext i1 @ICmpSGE(i32 %x) nounwind uwtable readnone sanitize_memory {
   ret i1 %1
 }
 
-; CHECK: @ICmpSGE
+; CHECK-LABEL: @ICmpSGE
 ; CHECK: icmp slt
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: icmp sge
@@ -414,7 +414,7 @@ define zeroext i1 @ICmpSGT(i32 %x) nounwind uwtable readnone sanitize_memory {
   ret i1 %1
 }
 
-; CHECK: @ICmpSGT
+; CHECK-LABEL: @ICmpSGT
 ; CHECK: icmp slt
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: icmp sgt
@@ -426,7 +426,7 @@ define zeroext i1 @ICmpSLE(i32 %x) nounwind uwtable readnone sanitize_memory {
   ret i1 %1
 }
 
-; CHECK: @ICmpSLE
+; CHECK-LABEL: @ICmpSLE
 ; CHECK: icmp slt
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: icmp sle
@@ -442,7 +442,7 @@ define <2 x i1> @ICmpSLT_vector(<2 x i32*> %x) nounwind uwtable readnone sanitiz
   ret <2 x i1> %1
 }
 
-; CHECK: @ICmpSLT_vector
+; CHECK-LABEL: @ICmpSLT_vector
 ; CHECK: icmp slt <2 x i64>
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: icmp slt <2 x i32*>
@@ -459,7 +459,7 @@ entry:
   ret i1 %cmp
 }
 
-; CHECK: @ICmpUGTConst
+; CHECK-LABEL: @ICmpUGTConst
 ; CHECK: icmp ugt i32
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: icmp ugt i32
@@ -478,7 +478,7 @@ define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory {
   ret i32 %1
 }
 
-; CHECK: @ShadowLoadAlignmentLarge
+; CHECK-LABEL: @ShadowLoadAlignmentLarge
 ; CHECK: load volatile i32, i32* {{.*}} align 64
 ; CHECK: load i32, i32* {{.*}} align 64
 ; CHECK: ret i32
@@ -489,7 +489,7 @@ define i32 @ShadowLoadAlignmentSmall() nounwind uwtable sanitize_memory {
   ret i32 %1
 }
 
-; CHECK: @ShadowLoadAlignmentSmall
+; CHECK-LABEL: @ShadowLoadAlignmentSmall
 ; CHECK: load volatile i32, i32* {{.*}} align 2
 ; CHECK: load i32, i32* {{.*}} align 2
 ; CHECK-ORIGINS: load i32, i32* {{.*}} align 4
@@ -505,7 +505,7 @@ define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) sanitize_memory {
   ret i32 %x
 }
 
-; CHECK: @ExtractElement
+; CHECK-LABEL: @ExtractElement
 ; CHECK: extractelement
 ; CHECK: call void @__msan_warning
 ; CHECK: extractelement
@@ -516,7 +516,7 @@ define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) sanitize_memor
   ret <4 x i32> %vec1
 }
 
-; CHECK: @InsertElement
+; CHECK-LABEL: @InsertElement
 ; CHECK: insertelement
 ; CHECK: call void @__msan_warning
 ; CHECK: insertelement
@@ -528,7 +528,7 @@ define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) sanitize_memory
   ret <4 x i32> %vec2
 }
 
-; CHECK: @ShuffleVector
+; CHECK-LABEL: @ShuffleVector
 ; CHECK: shufflevector
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: shufflevector
@@ -543,7 +543,7 @@ define i32 @BSwap(i32 %x) nounwind uwtable readnone sanitize_memory {
 
 declare i32 @llvm.bswap.i32(i32) nounwind readnone
 
-; CHECK: @BSwap
+; CHECK-LABEL: @BSwap
 ; CHECK-NOT: call void @__msan_warning
 ; CHECK: @llvm.bswap.i32
 ; CHECK-NOT: call void @__msan_warning
@@ -561,7 +561,7 @@ define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable sanitize_me
 
 declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
 
-; CHECK: @StoreIntrinsic
+; CHECK-LABEL: @StoreIntrinsic
 ; CHECK-NOT: br
 ; CHECK-NOT: = or
 ; CHECK: store <4 x i32> {{.*}} align 1
@@ -578,7 +578,7 @@ define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable sanitize_memory {
 
 declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
 
-; CHECK: @LoadIntrinsic
+; CHECK-LABEL: @LoadIntrinsic
 ; CHECK: load <16 x i8>, <16 x i8>* {{.*}} align 1
 ; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32, i32* {{.*}}
 ; CHECK-NOT: br
@@ -600,7 +600,7 @@ define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitiz
 
 declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
 
-; CHECK: @Paddsw128
+; CHECK-LABEL: @Paddsw128
 ; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
 ; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls
 ; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
@@ -623,7 +623,7 @@ define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable sanitize_memo
   ret <8 x i8*> %x
 }
 
-; CHECK: @VectorOfPointers
+; CHECK-LABEL: @VectorOfPointers
 ; CHECK: load <8 x i8*>, <8 x i8*>*
 ; CHECK: load <8 x i64>, <8 x i64>*
 ; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls
@@ -638,7 +638,7 @@ define void @VACopy(i8* %p1, i8* %p2) nounwind uwtable sanitize_memory {
   ret void
 }
 
-; CHECK: @VACopy
+; CHECK-LABEL: @VACopy
 ; CHECK: call void @llvm.memset.p0i8.i64({{.*}}, i8 0, i64 24, i32 8, i1 false)
 ; CHECK: ret void
 
@@ -661,7 +661,7 @@ entry:
   ret void
 }
 
-; CHECK: @VAStart
+; CHECK-LABEL: @VAStart
 ; CHECK: call void @llvm.va_start
 ; CHECK-NOT: @__msan_va_arg_tls
 ; CHECK-NOT: @__msan_va_arg_overflow_size_tls
@@ -677,7 +677,7 @@ entry:
   ret void
 }
 
-; CHECK: @VolatileStore
+; CHECK-LABEL: @VolatileStore
 ; CHECK-NOT: @__msan_warning
 ; CHECK: ret void
 
@@ -700,7 +700,7 @@ if.end:                                           ; preds = %entry, %if.then
 
 declare void @bar()
 
-; CHECK: @NoSanitizeMemory
+; CHECK-LABEL: @NoSanitizeMemory
 ; CHECK-NOT: @__msan_warning
 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls
 ; CHECK-NOT: @__msan_warning
@@ -719,7 +719,7 @@ entry:
 
 declare i32 @NoSanitizeMemoryAllocaHelper(i32* %p)
 
-; CHECK: @NoSanitizeMemoryAlloca
+; CHECK-LABEL: @NoSanitizeMemoryAlloca
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 4, i32 4, i1 false)
 ; CHECK: call i32 @NoSanitizeMemoryAllocaHelper(i32*
 ; CHECK: ret i32
@@ -736,7 +736,7 @@ entry:
 
 declare i32 @NoSanitizeMemoryUndefHelper(i32 %x)
 
-; CHECK: @NoSanitizeMemoryAlloca
+; CHECK-LABEL: @NoSanitizeMemoryUndef
 ; CHECK: store i32 0, i32* {{.*}} @__msan_param_tls
 ; CHECK: call i32 @NoSanitizeMemoryUndefHelper(i32 undef)
 ; CHECK: ret i32
@@ -790,7 +790,7 @@ entry:
   ret <2 x i64> %b
 }
 
-; CHECK: @ArgumentShadowAlignment
+; CHECK-LABEL: @ArgumentShadowAlignment
 ; CHECK: load <2 x i64>, <2 x i64>* {{.*}} @__msan_param_tls {{.*}}, align 8
 ; CHECK: store <2 x i64> {{.*}} @__msan_retval_tls {{.*}}, align 8
 ; CHECK: ret <2 x i64>
@@ -847,7 +847,7 @@ entry:
 ; "undef" and the first 2 structs go to general purpose registers;
 ; the third struct goes to the overflow area byval
 
-; CHECK: @VAArgStruct
+; CHECK-LABEL: @VAArgStruct
 ; undef
 ; CHECK: store i32 -1, i32* {{.*}}@__msan_va_arg_tls {{.*}}, align 8
 ; first struct through general purpose registers
diff --git a/test/Instrumentation/MemorySanitizer/return_from_main.ll b/test/Instrumentation/MemorySanitizer/return_from_main.ll
index 81dc88834db..82e2d13bc09 100644
--- a/test/Instrumentation/MemorySanitizer/return_from_main.ll
+++ b/test/Instrumentation/MemorySanitizer/return_from_main.ll
@@ -10,7 +10,7 @@ entry:
 
 declare i32 @f() sanitize_memory
 
-; CHECK: @main
+; CHECK-LABEL: @main
 ; CHECK: call i32 @f()
 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls
 ; CHECK: br i1
diff --git a/test/Instrumentation/MemorySanitizer/store-origin.ll b/test/Instrumentation/MemorySanitizer/store-origin.ll
index ba5651ecf4b..d81c7ed229f 100644
--- a/test/Instrumentation/MemorySanitizer/store-origin.ll
+++ b/test/Instrumentation/MemorySanitizer/store-origin.ll
@@ -52,7 +52,7 @@ attributes #1 = { nounwind readnone }
 !22 = !DILocation(line: 3, scope: !4)
 
 
-; CHECK: @Store
+; CHECK-LABEL: @Store
 ; CHECK: load {{.*}} @__msan_param_tls
 ; CHECK: [[ORIGIN:%[01-9a-z]+]] = load {{.*}} @__msan_param_origin_tls
 ; CHECK: store {{.*}}!dbg ![[DBG:[01-9]+]]
diff --git a/test/Instrumentation/MemorySanitizer/unreachable.ll b/test/Instrumentation/MemorySanitizer/unreachable.ll
index e9a79ce0d0e..ac5aea9a077 100644
--- a/test/Instrumentation/MemorySanitizer/unreachable.ll
+++ b/test/Instrumentation/MemorySanitizer/unreachable.ll
@@ -18,7 +18,7 @@ exit:
   ret i32 %z
 }
 
-; CHECK: @Func
+; CHECK-LABEL: @Func
 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls
 ; CHECK: ret i32 42
 
@@ -34,6 +34,6 @@ xxx:
   br label %zzz
 }
 
-; CHECK: @UnreachableLoop
+; CHECK-LABEL: @UnreachableLoop
 ; CHECK: store i32 0, {{.*}} @__msan_retval_tls
 ; CHECK: ret i32 0
diff --git a/test/Instrumentation/MemorySanitizer/vector_cvt.ll b/test/Instrumentation/MemorySanitizer/vector_cvt.ll
index a7d5f211501..55e91c74a31 100644
--- a/test/Instrumentation/MemorySanitizer/vector_cvt.ll
+++ b/test/Instrumentation/MemorySanitizer/vector_cvt.ll
@@ -15,7 +15,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: @test_cvtsd2si
+; CHECK-LABEL: @test_cvtsd2si
 ; CHECK: [[S:%[_01-9a-z]+]] = extractelement <2 x i64> {{.*}}, i32 0
 ; CHECK: icmp ne {{.*}}[[S]], 0
 ; CHECK: br
@@ -33,7 +33,7 @@ entry:
   ret <2 x double> %0
 }
 
-; CHECK: @test_cvtsi2sd
+; CHECK-LABEL: @test_cvtsi2sd
 ; CHECK: [[Sa:%[_01-9a-z]+]] = load i32, i32* {{.*}} @__msan_param_tls
 ; CHECK: [[Sout0:%[_01-9a-z]+]] = insertelement <2 x i64> <i64 -1, i64 -1>, i64 {{.*}}, i32 1
 ; Clear low half of result shadow
@@ -54,7 +54,7 @@ entry:
   ret x86_mmx %0
 }
 
-; CHECK: @test_cvtps2pi
+; CHECK-LABEL: @test_cvtps2pi
 ; CHECK: extractelement <4 x i32> {{.*}}, i32 0
 ; CHECK: extractelement <4 x i32> {{.*}}, i32 1
 ; CHECK: [[S:%[_01-9a-z]+]] = or i32
diff --git a/test/Instrumentation/MemorySanitizer/vector_shift.ll b/test/Instrumentation/MemorySanitizer/vector_shift.ll
index 91e4bd53c6a..d7b47f011b1 100644
--- a/test/Instrumentation/MemorySanitizer/vector_shift.ll
+++ b/test/Instrumentation/MemorySanitizer/vector_shift.ll
@@ -25,7 +25,7 @@ entry:
   ret i64 %6
 }
 
-; CHECK: @test_mmx
+; CHECK-LABEL: @test_mmx
 ; CHECK: = icmp ne i64 {{.*}}, 0
 ; CHECK: [[C:%.*]] = sext i1 {{.*}} to i64
 ; CHECK: [[A:%.*]] = call x86_mmx @llvm.x86.mmx.psll.d(
@@ -41,7 +41,7 @@ entry:
   ret <8 x i16> %0
 }
 
-; CHECK: @test_sse2_scalar
+; CHECK-LABEL: @test_sse2_scalar
 ; CHECK: = icmp ne i32 {{.*}}, 0
 ; CHECK: = sext i1 {{.*}} to i128
 ; CHECK: = bitcast i128 {{.*}} to <8 x i16>
@@ -57,7 +57,7 @@ entry:
   ret <8 x i16> %0
 }
 
-; CHECK: @test_sse2
+; CHECK-LABEL: @test_sse2
 ; CHECK: = bitcast <8 x i16> {{.*}} to i128
 ; CHECK: = trunc i128 {{.*}} to i64
 ; CHECK: = icmp ne i64 {{.*}}, 0
@@ -77,7 +77,7 @@ entry:
   ret <4 x i32> %0
 }
 
-; CHECK: @test_avx2
+; CHECK-LABEL: @test_avx2
 ; CHECK: = icmp ne <4 x i32> {{.*}}, zeroinitializer
 ; CHECK: = sext <4 x i1> {{.*}} to <4 x i32>
 ; CHECK: = call <4 x i32> @llvm.x86.avx2.psllv.d(
@@ -91,7 +91,7 @@ entry:
   ret <8 x i32> %0
 }
 
-; CHECK: @test_avx2_256
+; CHECK-LABEL: @test_avx2_256
 ; CHECK: = icmp ne <8 x i32> {{.*}}, zeroinitializer
 ; CHECK: = sext <8 x i1> {{.*}} to <8 x i32>
 ; CHECK: = call <8 x i32> @llvm.x86.avx2.psllv.d.256(