From: Jacob Chen <jacob2.chen@rock-chips.com>
Date: Fri, 9 Dec 2016 06:40:18 +0000 (+0800)
Subject: UPSTREAM: arm: dts: rockchip: add reset node for the exist saradc SoCs
X-Git-Tag: firefly_0821_release~1104
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=31c917aebeae990c9a5b834d84ecdce77def93ca;p=firefly-linux-kernel-4.4.55.git

UPSTREAM: arm: dts: rockchip: add reset node for the exist saradc SoCs

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Change-Id: Iaafd41b163ebd853278baea5c1c10dc82c54792b
 (cherry picked from commit 3d4267a5a3a4b7619b80ad1839d8b3bedd8b7a8d)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
---

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index e5bedf896874..4f48c5011982 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -283,6 +283,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 9a2f947778a5..66296fd497d9 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -409,6 +409,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};