From: hxy Date: Wed, 16 Feb 2011 02:04:28 +0000 (+0800) Subject: add ddr auto powerdown in DDR_Initand change comment from chinese to english X-Git-Tag: firefly_0821_release~10763 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=326b52a37d4deb21988386a9c1f2bcccbdbf422d;p=firefly-linux-kernel-4.4.55.git add ddr auto powerdown in DDR_Initand change comment from chinese to english --- diff --git a/arch/arm/mach-rk29/ddr.c b/arch/arm/mach-rk29/ddr.c index 42896358579a..657b59e9acea 100644 --- a/arch/arm/mach-rk29/ddr.c +++ b/arch/arm/mach-rk29/ddr.c @@ -1,13 +1,12 @@ /**************************************************************** * CopyRight(C) 2010 by Rock-Chip Fuzhou * All Rights Reserved -* ÎļþÃû:ddr.c -* ÃèÊö: ddr driver implement -* ×÷Õß:hcy -* ´´½¨ÈÕÆÚ:2011-01-04 -* ¸ü¸Ä¼Ç¼: -* $Log: ddr.c,v $ -* µ±Ç°°æ±¾:1.00 20110104 hcy Ìá½»³õʼ°æ±¾ +* File name :ddr.c +* Description: ddr driver implement +* Author :hcy +* Create date :2011-01-04 +* Change log: +* Current version:1.00 20110104 hcy ****************************************************************/ #include @@ -33,7 +32,7 @@ #include -// save_sp ±ØÐ붨ÒåΪ¾²Ì¬È«¾Ö±äÁ¿ +// save_sp must be static global variable static unsigned long save_sp; @@ -369,7 +368,7 @@ typedef enum tagDDRDLLMode static __sramdata u32 bFreqRaise; -static __sramdata u32 capability; //µ¥¸öCSµÄÈÝÁ¿ +static __sramdata u32 capability; // one chip cs capability //DDR2 static __sramdata u32 tRFC; @@ -386,8 +385,8 @@ static __sramdata u32 tXP; /**************************************************************************** -ÄÚ²¿sram µÄus ÑÓʱº¯Êý -¼Ù¶¨cpu ×î¸ßƵÂÊ1.2 GHz +Internal sram us delay function +Cpu highest frequency is 1.2 GHz 1 cycle = 1/1.2 ns 1 us = 1000 ns = 1000 * 1.2 cycles = 1200 cycles *****************************************************************************/ @@ -471,15 +470,14 @@ u32 __sramfunc GetDDRCL(u32 newMHz) } } -/****************************************************************/ -//º¯ÊýÃû:SDRAM_EnterSelfRefresh -//ÃèÊö:SDRAM½øÈë×ÔË¢ÐÂģʽ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:(1)ϵͳÍêÈ«idleºó²ÅÄܽøÈë×ÔË¢ÐÂģʽ£¬½øÈë×Ôˢкó²»ÄÜÔÙ·ÃÎÊSDRAM -// (2)Òª½øÈë×ÔË¢ÐÂģʽ£¬±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýËùµ÷Óõ½µÄËùÓдúÂë²»ÔÚSDRAMÉÏ -/****************************************************************/ +/*------------------------------------------------------------------- +Name : EnterDDRSelfRefresh +Desc : DDR enter self refresh +Params : +Return : +Notes : 1. ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr + 2. ddr enter sel-refresh code must not be in ddr +-------------------------------------------------------------------*/ void __sramfunc EnterDDRSelfRefresh(void) { pDDR_Reg->CCR &= ~HOSTEN; //disable host port @@ -489,15 +487,14 @@ void __sramfunc EnterDDRSelfRefresh(void) delayus(10); } -/****************************************************************/ -//º¯ÊýÃû:SDRAM_ExitSelfRefresh -//ÃèÊö:SDRAMÍ˳ö×ÔË¢ÐÂģʽ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:(1)SDRAMÔÚ×ÔË¢ÐÂģʽºó²»Äܱ»·ÃÎÊ£¬±ØÐëÏÈÍ˳ö×ÔË¢ÐÂģʽ -// (2)±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýµÄ´úÂë²»ÔÚSDRAMÉÏ -/****************************************************************/ +/*------------------------------------------------------------------- +Name : ExitDDRSelfRefresh +Desc : DDR exit self refresh +Params : +Return : +Notes : 1. ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr + 2. ddr enter sel-refresh code must not be in ddr +-------------------------------------------------------------------*/ void __sramfunc ExitDDRSelfRefresh(void) { @@ -515,12 +512,12 @@ void __sramfunc ExitDDRSelfRefresh(void) /*------------------------------------------------------------------- Name : PLLGetAHBFreq -Desc : »ñÈ¡DDRµÄƵÂÊ +Desc : get DDR frequency Params : -Return : DDRƵÂÊ, KHz Ϊµ¥Î» +Return : DDR frequency, min is KHz Notes : -------------------------------------------------------------------*/ -static u32 PLLGetDDRFreq(void) +static u32 PLLGetDDRFreq(void) // ??????????????? need to check it by huangtao , Is DPLL only used by DDR? { u32 nr; u32 nf; @@ -893,15 +890,13 @@ DDR_CONFIG_T ddrConfig[3][10] = { } }; - -/****************************************************************/ -//º¯ÊýÃû:SDRAM_Init -//ÃèÊö:DDR ³õʼ»¯ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ: -/****************************************************************/ +/*------------------------------------------------------------------- +Name : DDR_Init +Desc : ddr initialize +Params : +Return : +Notes : +-------------------------------------------------------------------*/ u32 ddrDataTraining[16]; void DDR_Init(void) { @@ -916,20 +911,16 @@ void DDR_Init(void) u32 bank; u32 n; - //ËãÎïÀí¶ÔÆëµØÖ· - n = (unsigned long)ddrDataTraining; - printk("\n#################### VA = 0x%x\n", n); + // caculate aglined physical address addr = __pa((unsigned long)ddrDataTraining); - printk("#################### PA = 0x%x", addr); if(addr&0x1F) { addr += (32-(addr&0x1F)); } addr -= 0x60000000; - printk("#################### PA aligned = 0x%x\n", addr); - //ËãÊý¾ÝÏß¿í + // caculate data width bw = ((((pDDR_Reg->DCR >> 7) & 0x7)+1)>>1); - //²é³öcol£¬row£¬bank + // find out col£¬row£¬bank for(n=0;n<10; n++) { if(ddrConfig[(pDDR_Reg->DCR & 0x3)][n].config == (pDDR_Reg->DCR & 0x7c)) @@ -946,8 +937,8 @@ void DDR_Init(void) { //ASSERT } - printk("#################### bw = 0x%x, col = 0x%x, row = 0x%x, bank = 0x%x\n", bw, col, row, bank); - //¸ù¾Ý²»Í¬µÄµØÖ·Ó³É䷽ʽ£¬Ëã³öDTAR¼Ä´æÆ÷µÄÅäÖà + + // according different address mapping, caculate DTAR register value value = pDDR_Reg->DTAR; value &= ~(0x7FFFFFFF); switch(pDDR_Reg->DCR & (0x3<<14)) @@ -975,16 +966,15 @@ void DDR_Init(void) value |= ((addr>>(bw+col+row)) & ((0x1<DTAR = value; if(memType == DDRII) { - pDDR_Reg->ALPMR = LPPERIOD_POWER_DOWN(0xFF); /* | AUTOPD;*/ + pDDR_Reg->ALPMR = LPPERIOD_POWER_DOWN(0xFF)|AUTOPD; } else { @@ -1001,8 +991,17 @@ void DDR_Init(void) DDRPreUpdateTiming(MHz); DDRUpdateRef(); DDRUpdateTiming(); + } +/*------------------------------------------------------------------- +Name : DDR_ChangeFreq +Desc : change ddr frequency +Params : +Return : +Notes : close interrupt before call it + open interrupt after call it +-------------------------------------------------------------------*/ void DDR_ChangeFreq(u32 DDRoldMHz, u32 DDRnewMHz) { @@ -1017,15 +1016,14 @@ void DDR_ChangeFreq(u32 DDRoldMHz, u32 DDRnewMHz) //////////////////////////////////////////////////////////////////////////////////// -/****************************************************************/ -//º¯ÊýÃû:SDRAM_EnterSelfRefresh -//ÃèÊö:SDRAM½øÈë×ÔË¢ÐÂģʽ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:(1)ϵͳÍêÈ«idleºó²ÅÄܽøÈë×ÔË¢ÐÂģʽ£¬½øÈë×Ôˢкó²»ÄÜÔÙ·ÃÎÊSDRAM -// (2)Òª½øÈë×ÔË¢ÐÂģʽ£¬±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýËùµ÷Óõ½µÄËùÓдúÂë²»ÔÚSDRAMÉÏ -/****************************************************************/ +/*------------------------------------------------------------------- +Name : DDR_EnterSelfRefresh +Desc : DDR enter self refresh call in ddr +Params : +Return : +Notes : 1. ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr + 2. ddr enter sel-refresh code must not be in ddr +-------------------------------------------------------------------*/ void __sramfunc DDR_EnterSelfRefresh(void) { EnterDDRSelfRefresh(); @@ -1041,15 +1039,14 @@ void __sramfunc DDR_EnterSelfRefresh(void) #endif } -/****************************************************************/ -//º¯ÊýÃû:SDRAM_ExitSelfRefresh -//ÃèÊö:SDRAMÍ˳ö×ÔË¢ÐÂģʽ -//²ÎÊý˵Ã÷: -//·µ»ØÖµ: -//Ïà¹ØÈ«¾Ö±äÁ¿: -//×¢Òâ:(1)SDRAMÔÚ×ÔË¢ÐÂģʽºó²»Äܱ»·ÃÎÊ£¬±ØÐëÏÈÍ˳ö×ÔË¢ÐÂģʽ -// (2)±ØÐë±£Ö¤ÔËÐÐʱÕâ¸öº¯ÊýµÄ´úÂë²»ÔÚSDRAMÉÏ -/****************************************************************/ +/*------------------------------------------------------------------- +Name : DDR_ExitSelfRefresh +Desc : DDR exit self refresh +Params : +Return : +Notes : 1. ddr enter sel-refresh must be after system enter idle ,after ddr enter sel-refresh must not access ddr + 2. ddr enter sel-refresh code must not be in ddr +-------------------------------------------------------------------*/ void __sramfunc DDR_ExitSelfRefresh(void) { #if 1 @@ -1076,7 +1073,7 @@ void __sramfunc DDR_ExitSelfRefresh(void) "mcr p15,0,%2,c10,c0,1\n\t" ::"r"(vaddr) , "r"(0x00000001), "r"(0x08400000)); } -// ¿¼ÂÇcpu Ԥȡ¡¢mmu cache +// consider cpu prefetch¡¢mmu cache static void __sramfunc do_selfrefreshtest(void) { volatile u32 n;