From: Chris Lattner <sabre@nondot.org>
Date: Sat, 4 Feb 2006 07:48:46 +0000 (+0000)
Subject: fix a bug in my last checkin
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=329a515fe758b36bd443279b0c4ee690517159b3;p=oota-llvm.git

fix a bug in my last checkin


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25965 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index cddeddd9b82..8f0dc01cd14 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -40,12 +40,12 @@ bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(2).getReg();
       return true;
-    } else if (MI.getOperand (2).getReg() == V8::G0) {
+    } else if (MI.getOperand(2).getReg() == V8::G0) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(1).getReg();
       return true;
     }
-  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri &&
+  } else if ((MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) &&
              isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.cpp b/lib/Target/SparcV8/SparcV8InstrInfo.cpp
index cddeddd9b82..8f0dc01cd14 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.cpp
@@ -40,12 +40,12 @@ bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(2).getReg();
       return true;
-    } else if (MI.getOperand (2).getReg() == V8::G0) {
+    } else if (MI.getOperand(2).getReg() == V8::G0) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(1).getReg();
       return true;
     }
-  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri &&
+  } else if ((MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) &&
              isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();