From: Bill Wendling <isanbard@gmail.com>
Date: Tue, 16 Nov 2010 23:44:49 +0000 (+0000)
Subject: Use the correct variable names so that the encodings will be correct.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3380f6a4d0f88fa27ac7112ffe0ad9b55f589828;p=oota-llvm.git

Use the correct variable names so that the encodings will be correct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 2c4d723caee..c06208e6ba4 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1870,9 +1870,9 @@ def : MnemonicAlias<"stm", "stmia">;
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                      reglist:$dsts, variable_ops),
+                                      reglist:$regs, variable_ops),
                      IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
-                     "ldmia${p}\t$Rn!, $dsts",
+                     "ldmia${p}\t$Rn!, $regs",
                      "$Rn = $wb", []> {
   let Inst{24-23} = 0b01;       // Increment After
   let Inst{21}    = 1;          // Writeback
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 03a6b4f3096..6582e96bb80 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2760,9 +2760,9 @@ let Defs =
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                        reglist:$dsts, variable_ops),
+                                        reglist:$regs, variable_ops),
                         IIC_iLoad_mBr,
-                        "ldmia${p}.w\t$Rn!, $dsts",
+                        "ldmia${p}.w\t$Rn!, $regs",
                         "$Rn = $wb", []> {
   bits<4>  Rn;
   bits<16> regs;