From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 13:55:51 +0000 (+0000)
Subject: Fix epic bug with invalid regclass for R0D
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=338cf05f16e3d0f1f0de1c0d8969f11bc7df1240;p=oota-llvm.git

Fix epic bug with invalid regclass for R0D

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75956 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td
index e047150d6a7..bdff54262f9 100644
--- a/lib/Target/SystemZ/SystemZRegisterInfo.td
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.td
@@ -144,7 +144,7 @@ def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
 /// Register classes
 def GR32 : RegisterClass<"SystemZ", [i32], 32,
    // Volatile registers
-  [R0D, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
+  [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
    // Frame pointer, sometimes allocable
    R11W,
    // Volatile, but not allocable