From: Dale Johannesen Date: Wed, 4 Feb 2009 20:06:27 +0000 (+0000) Subject: Remove non-DebugLoc versions of getLoad and getStore. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=33c960f523f2308482d5b2816af46a7ec90a6d3d;p=oota-llvm.git Remove non-DebugLoc versions of getLoad and getStore. Adjust the many callers of those versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 9f9ab4f498d..94c5a85d84b 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -576,9 +576,6 @@ public: /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. /// - SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr, - const Value *SV, int SVOffset, bool isVolatile=false, - unsigned Alignment=0); SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); @@ -588,11 +585,6 @@ public: unsigned Alignment=0); SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM); - SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT VT, SDValue Chain, - SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, - bool isVolatile=false, unsigned Alignment=0); SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType, MVT VT, SDValue Chain, SDValue Ptr, SDValue Offset, @@ -601,9 +593,6 @@ public: /// getStore - Helper function to build ISD::STORE nodes. /// - SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr, - const Value *SV, int SVOffset, bool isVolatile=false, - unsigned Alignment=0); SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index b0ab178a332..dc3b8eb8b75 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -556,6 +556,7 @@ void SelectionDAGLegalize::HandleOp(SDValue Op) { static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SelectionDAG &DAG, const TargetLowering &TLI) { bool Extend = false; + DebugLoc dl = CFP->getDebugLoc(); // If a FP immediate is precise when represented as a float and if the // target can do an extending load from float to double, we put it into @@ -591,11 +592,11 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); unsigned Alignment = 1 << cast(CPIdx)->getAlignment(); if (Extend) - return DAG.getExtLoad(ISD::EXTLOAD, CFP->getDebugLoc(), + return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, VT, false, Alignment); - return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, + return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index ebc67dd0b9d..435bcafe8e5 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3553,55 +3553,6 @@ SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, return SDValue(N, 0); } -SDValue -SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT VT, SDValue Chain, - SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, - bool isVolatile, unsigned Alignment) { - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - if (VT == EVT) { - ExtType = ISD::NON_EXTLOAD; - } else if (ExtType == ISD::NON_EXTLOAD) { - assert(VT == EVT && "Non-extending load from different memory type!"); - } else { - // Extending load. - if (VT.isVector()) - assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && - "Invalid vector extload!"); - else - assert(EVT.bitsLT(VT) && - "Should only be an extending load, not truncating!"); - assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && - "Cannot sign/zero extend a FP/Vector load!"); - assert(VT.isInteger() == EVT.isInteger() && - "Cannot convert from FP to Int or Int -> FP!"); - } - - bool Indexed = AM != ISD::UNINDEXED; - assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && - "Unindexed load with an offset!"); - - SDVTList VTs = Indexed ? - getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); - SDValue Ops[] = { Chain, Ptr, Offset }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); - ID.AddInteger(EVT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, - Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType, MVT VT, SDValue Chain, @@ -3651,15 +3602,6 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, return SDValue(N, 0); } -SDValue SelectionDAG::getLoad(MVT VT, - SDValue Chain, SDValue Ptr, - const Value *SV, int SVOffset, - bool isVolatile, unsigned Alignment) { - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, - SV, SVOffset, VT, isVolatile, Alignment); -} - SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, @@ -3691,33 +3633,6 @@ SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, LD->isVolatile(), LD->getAlignment()); } -SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, - SDValue Ptr, const Value *SV, int SVOffset, - bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); - - if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); - - SDVTList VTs = getVTList(MVT::Other); - SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); - SDValue Ops[] = { Chain, Val, Ptr, Undef }; - FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); - ID.AddInteger(VT.getRawBits()); - ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, - isVolatile, Alignment)); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - SDNode *N = NodeAllocator.Allocate(); - new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, - VT, SV, SVOffset, Alignment, isVolatile); - CSEMap.InsertNode(N, IP); - AllNodes.push_back(N); - return SDValue(N, 0); -} - SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 504a5c4e72a..a6c4d8ba9d8 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -403,7 +403,8 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { TheCall->getCallingConv() == CallingConv::Fast) && "unknown calling convention"); SDValue Callee = TheCall->getCallee(); - unsigned NumOps = TheCall->getNumArgs(); + unsigned NumOps = TheCall->getNumArgs(); + DebugLoc dl = TheCall->getDebugLoc(); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. @@ -458,25 +459,25 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { break; case MVT::f32: RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], - DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg))); break; case MVT::i64: { - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, DAG.getConstant(0, getPointerTy())); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, DAG.getConstant(1, getPointerTy())); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); if (ObjGPRs == 2) RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); else { SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, NULL, 0)); } break; } case MVT::f64: { - SDValue Cvt = DAG.getNode(ARMISD::FMRRD, + SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); @@ -485,8 +486,8 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { Cvt.getValue(1))); else { SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Cvt.getValue(1), PtrOff, NULL, 0)); } break; @@ -495,8 +496,8 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { } else { assert(ObjSize != 0); SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); } NumGPRs += ObjGPRs; @@ -504,15 +505,15 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -538,9 +539,11 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); + Callee = DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); + Callee = DAG.getNode(ARMISD::PIC_ADD, dl, + getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { @@ -555,9 +558,11 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); + Callee = DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); + Callee = DAG.getNode(ARMISD::PIC_ADD, dl, + getPointerTy(), Callee, PICLabel); } else Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); } @@ -576,7 +581,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { } if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK - Chain = DAG.getCopyToReg(Chain, ARM::LR, + Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); InFlag = Chain.getValue(1); } @@ -594,7 +599,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -611,25 +616,27 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { case MVT::Other: break; case MVT::i32: - Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0, + MVT::i32, InFlag).getValue(1); ResultVals.push_back(Chain.getValue(0)); if (TheCall->getNumRetVals() > 1 && TheCall->getRetValType(1) == MVT::i32) { // Returns a i64 value. - Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R1, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals.push_back(Chain.getValue(0)); } break; case MVT::f32: - Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); - ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, + Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0, + MVT::i32, InFlag).getValue(1); + ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Chain.getValue(0))); break; case MVT::f64: { - SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); - SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); - ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); + SDValue Lo = DAG.getCopyFromReg(Chain, dl, ARM::R0, MVT::i32, InFlag); + SDValue Hi = DAG.getCopyFromReg(Lo, dl, ARM::R1, MVT::i32, Lo.getValue(2)); + ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi)); break; } } @@ -638,7 +645,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { return Chain; ResultVals.push_back(Chain); - SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); + SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl); return Res.getValue(Op.getResNo()); } @@ -721,6 +728,7 @@ static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) { + DebugLoc dl = GA->getDebugLoc(); MVT PtrVT = getPointerTy(); unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = @@ -728,11 +736,11 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, PCAdj, "tlsgd", true); SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); - Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); + Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0); SDValue Chain = Argument.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); + Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); // call __tls_get_addr. ArgListTy Args; @@ -744,8 +752,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, std::pair CallResult = LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, CallingConv::C, false, - DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, - DebugLoc::getUnknownLoc()); + DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); return CallResult.first; } @@ -755,11 +762,12 @@ SDValue ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, SelectionDAG &DAG) { GlobalValue *GV = GA->getGlobal(); + DebugLoc dl = GA->getDebugLoc(); SDValue Offset; SDValue Chain = DAG.getEntryNode(); MVT PtrVT = getPointerTy(); // Get the Thread Pointer - SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); + SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); if (GV->isDeclaration()){ // initial exec model @@ -769,25 +777,25 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, PCAdj, "gottpoff", true); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); Chain = Offset.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); + Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } else { // local exec model ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); - Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. - return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); + return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); } SDValue @@ -807,6 +815,7 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); if (RelocM == Reloc::PIC_) { @@ -815,17 +824,18 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), + CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); - Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); + Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); if (!UseGOTOFF) - Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); return Result; } else { SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); } } @@ -843,6 +853,7 @@ static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); @@ -860,15 +871,15 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, } CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); if (RelocM == Reloc::PIC_) { SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); + Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } if (IsIndirect) - Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); + Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); return Result; } @@ -878,15 +889,16 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, assert(Subtarget->isTargetELF() && "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); MVT PtrVT = getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, ARMCP::CPValue, PCAdj); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); - SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); + SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); - return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); + return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { @@ -903,15 +915,16 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, unsigned VarArgsFrameIndex) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, unsigned ArgNo, unsigned &NumGPRs, - unsigned &ArgOffset) { + unsigned &ArgOffset, DebugLoc dl) { MachineFunction &MF = DAG.getMachineFunction(); MVT ObjectVT = Op.getValue(ArgNo).getValueType(); SDValue Root = Op.getOperand(0); @@ -936,20 +949,20 @@ static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, if (ObjGPRs == 1) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); if (ObjectVT == MVT::f32) - ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); + ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); } else if (ObjGPRs == 2) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); + ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); - SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); - ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); + ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); } NumGPRs += ObjGPRs; @@ -958,11 +971,11 @@ static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); if (ObjGPRs == 0) - ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgValue = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); else { - SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); + SDValue ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); - ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); + ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); } ArgOffset += ObjSize; // Move on to the next argument. @@ -975,13 +988,14 @@ SDValue ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { std::vector ArgValues; SDValue Root = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. unsigned NumArgs = Op.getNode()->getNumValues()-1; for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, - NumGPRs, ArgOffset)); + NumGPRs, ArgOffset, dl)); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; if (isVarArg) { @@ -1009,14 +1023,14 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { for (; NumGPRs < 4; ++NumGPRs) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); - FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, + FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getConstant(4, getPointerTy())); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); } else // This will point to the next argument passed via stack. @@ -1026,7 +1040,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1194,6 +1208,7 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { SDValue Chain = Op.getOperand(0); SDValue Table = Op.getOperand(1); SDValue Index = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); MVT PTy = getPointerTy(); JumpTableSDNode *JT = cast(Table); @@ -1201,15 +1216,15 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); - Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); - SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); + Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; - Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, + Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl, Chain, Addr, NULL, 0); Chain = Addr.getValue(1); if (isPIC) - Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); - return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); + Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); + return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); } static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 675cdbff1ea..cf6ae60790c 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -219,6 +219,7 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, MachineFrameInfo *MFI = MF.getFrameInfo(); std::vector ArgValues; SDValue Root = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA @@ -240,17 +241,17 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, case MVT::f64: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F8RCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT); break; case MVT::f32: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F4RCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT); break; case MVT::i64: args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], &Alpha::GPRCRegClass); - ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64); + ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64); break; } } else { //more args @@ -260,7 +261,7 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, // Create the SelectionDAG nodes corresponding to a load //from this parameter SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); } @@ -273,28 +274,28 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, for (int i = 0; i < 6; ++i) { if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); - SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); + SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); if (i == 0) VarArgsBase = FI; SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); + LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0)); if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); - argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); + argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); SDFI = DAG.getFrameIndex(FI, MVT::i64); - LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); + LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0)); } //Set up a token factor with all the stack traffic - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size()); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -622,13 +623,14 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { void AlphaTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) { + DebugLoc dl = N->getDebugLoc(); assert(N->getValueType(0) == MVT::i32 && N->getOpcode() == ISD::VAARG && "Unknown node to custom promote!"); SDValue Chain, DataPtr; LowerVAARG(N, Chain, DataPtr, DAG); - SDValue Res = DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0); + SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0); Results.push_back(Res); Results.push_back(SDValue(Res.getNode(), 1)); } diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index ea767586b06..08cc8d0d057 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -249,6 +249,7 @@ public: SDNode *emitBuildVector(SDValue build_vec) { MVT vecVT = build_vec.getValueType(); SDNode *bvNode = build_vec.getNode(); + DebugLoc dl = bvNode->getDebugLoc(); // Check to see if this vector can be represented as a CellSPU immediate // constant by invoking all of the instruction selection predicates: @@ -279,7 +280,7 @@ public: SDValue CGPoolOffset = SPU::LowerConstantPool(CPIdx, *CurDAG, SPUtli.getSPUTargetMachine()); - return SelectCode(CurDAG->getLoad(build_vec.getValueType(), + return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl, CurDAG->getEntryNode(), CGPoolOffset, PseudoSourceValue::getConstantPool(), 0, false, Alignment)); diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 9e48962cce7..0596a590152 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -507,6 +507,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); const valtype_map_s *vtm = getValueTypeMapEntry(InVT); + DebugLoc dl = Op.getDebugLoc(); switch (LN->getAddressingMode()) { case ISD::UNINDEXED: { @@ -553,7 +554,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { int64_t rotamt = -vtm->prefslot_byte; if (rotamt < 0) rotamt += 16; - rotate = DAG.getNode(ISD::ADD, PtrVT, + rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(rotamt, PtrVT)); } @@ -573,8 +574,8 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); - the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag); - basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT); + the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); + basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add , ) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. @@ -588,13 +589,13 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Offset the rotate amount by the basePtr and the preferred slot // byte offset - rotate = DAG.getNode(ISD::ADD, PtrVT, + rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(-vtm->prefslot_byte, PtrVT)); } // Re-emit as a v16i8 vector load - result = DAG.getLoad(MVT::v16i8, the_chain, basePtr, + result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), 16); @@ -602,27 +603,27 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { the_chain = result.getValue(1); // Rotate into the preferred slot: - result = DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v16i8, + result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8, result.getValue(0), rotate); // Convert the loaded v16i8 vector to the appropriate vector type // specified by the operand: MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits())); - result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT, - DAG.getNode(ISD::BIT_CONVERT, vecVT, result)); + result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, + DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result)); // Handle extending loads by extending the scalar result: if (ExtType == ISD::SEXTLOAD) { - result = DAG.getNode(ISD::SIGN_EXTEND, OutVT, result); + result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result); } else if (ExtType == ISD::ZEXTLOAD) { - result = DAG.getNode(ISD::ZERO_EXTEND, OutVT, result); + result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result); } else if (ExtType == ISD::EXTLOAD) { unsigned NewOpc = ISD::ANY_EXTEND; if (OutVT.isFloatingPoint()) NewOpc = ISD::FP_EXTEND; - result = DAG.getNode(NewOpc, OutVT, result); + result = DAG.getNode(NewOpc, dl, OutVT, result); } SDVTList retvts = DAG.getVTList(OutVT, MVT::Other); @@ -631,7 +632,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { the_chain }; - result = DAG.getNode(SPUISD::LDRESULT, retvts, + result = DAG.getNode(SPUISD::LDRESULT, dl, retvts, retops, sizeof(retops) / sizeof(retops[0])); return result; } @@ -663,6 +664,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { MVT VT = Value.getValueType(); MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + DebugLoc dl = Op.getDebugLoc(); unsigned alignment = SN->getAlignment(); switch (SN->getAddressingMode()) { @@ -719,8 +721,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // in a register. Note that this is done because we need to avoid // creating a 0(reg) d-form address due to the SPU's block loads. basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1); - the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag); - basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT); + the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); + basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); } else { // Convert the (add , ) to an indirect address, which // will likely be lowered as a reg(reg) x-form address. @@ -733,13 +735,13 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } // Insertion point is solely determined by basePtr's contents - insertEltOffs = DAG.getNode(ISD::ADD, PtrVT, + insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant(0, PtrVT)); } // Re-emit as a v16i8 vector load - alignLoadVec = DAG.getLoad(MVT::v16i8, the_chain, basePtr, + alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, SN->getSrcValue(), SN->getSrcValueOffset(), SN->isVolatile(), 16); @@ -771,15 +773,16 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { #endif SDValue insertEltOp = - DAG.getNode(SPUISD::SHUFFLE_MASK, vecVT, insertEltOffs); + DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs); SDValue vectorizeOp = - DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue); + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue); - result = DAG.getNode(SPUISD::SHUFB, vecVT, + result = DAG.getNode(SPUISD::SHUFB, dl, vecVT, vectorizeOp, alignLoadVec, - DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp)); + DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::v4i32, insertEltOp)); - result = DAG.getStore(the_chain, result, basePtr, + result = DAG.getStore(the_chain, dl, result, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), LN->getAlignment()); @@ -926,6 +929,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) SmallVector ArgValues; SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; + DebugLoc dl = Op.getDebugLoc(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); @@ -986,7 +990,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); - ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ++ArgRegIdx; } else { // We need to load the argument to a virtual register if we determined @@ -994,7 +998,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) // or we're forced to do vararg int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); + ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); ArgOffset += StackSlotSize; } @@ -1015,7 +1019,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8); - SDValue Store = DAG.getStore(Root, ArgVal, FIN, NULL, 0); + SDValue Store = DAG.getStore(Root, dl, ArgVal, FIN, NULL, 0); Root = Store.getOperand(0); MemOps.push_back(Store); @@ -1023,13 +1027,14 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) ArgOffset += StackSlotSize; } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor,MVT::Other,&MemOps[0],MemOps.size()); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + &MemOps[0], MemOps.size()); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()); } @@ -1056,6 +1061,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); + DebugLoc dl = TheCall->getDebugLoc(); // Handy pointer type MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -1086,7 +1092,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); switch (Arg.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); @@ -1098,7 +1104,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1107,7 +1113,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1120,7 +1126,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); ArgOffset += StackSlotSize; } break; @@ -1134,7 +1140,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (!MemOpChains.empty()) { // Adjust the stack pointer for the stack arguments. - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); } @@ -1142,8 +1148,8 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, - InFlag); + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -1207,7 +1213,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -1225,31 +1231,35 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { case MVT::Other: break; case MVT::i32: if (TheCall->getValueType(1) == MVT::i32) { - Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4, + MVT::i32, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals[1] = Chain.getValue(0); NumResults = 2; } else { - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; } break; case MVT::i64: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i64, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; break; case MVT::i128: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i128, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128, + InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; break; case MVT::f32: case MVT::f64: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0), + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; @@ -1260,7 +1270,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: - Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0), + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; @@ -1273,7 +1283,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals[NumResults++] = Chain; - SDValue Res = DAG.getMergeValues(ResultVals, NumResults); + SDValue Res = DAG.getMergeValues(ResultVals, NumResults, dl); return Res.getValue(Op.getResNo()); } diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index ff7ad901877..3031218b38f 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -554,6 +554,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, SDValue IA64TargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::GlobalTLSAddress: @@ -566,21 +567,21 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) { assert(0 && "Do not know how to return this many arguments!"); abort(); case 1: - AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); - AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS, + AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); + AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS, AR_PFSVal); - return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal); + return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal); case 3: { // Copy the result into the output register & restore ar.pfs MVT ArgVT = Op.getOperand(1).getValueType(); unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8; - AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); - Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), - SDValue()); - AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal, - Copy.getValue(1)); - return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, + AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64); + Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg, + Op.getOperand(1), SDValue()); + AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl, + IA64::AR_PFS, AR_PFSVal, Copy.getValue(1)); + return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal, AR_PFSVal.getValue(1)); } } @@ -589,24 +590,24 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::VAARG: { MVT VT = getPointerTy(); const Value *SV = cast(Op.getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), + SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1), SV, 0); // Increment the pointer, VAList, to the next vaarg - SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList, + SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList, DAG.getConstant(VT.getSizeInBits()/8, VT)); // Store the incremented VAList to the legalized pointer - VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, + VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr, Op.getOperand(1), SV, 0); // Load the actual argument out of the pointer VAList - return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 5af38bf4ab4..91174b60e17 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -468,6 +468,7 @@ LowerSELECT(SDValue Op, SelectionDAG &DAG) SDValue MipsTargetLowering:: LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast(Op)->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); @@ -478,21 +479,22 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) if (!isa(GV) && IsGlobalInSmallSection(GV)) { SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); - return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); + return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); } // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); } else { // Abicall relocations, TODO: make this cleaner. - SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); + SDValue ResNode = DAG.getLoad(MVT::i32, dl, + DAG.getEntryNode(), GA, NULL, 0); // On functions and global targets not internal linked only // a load from got/GP is necessary for PIC to work. if (!GV->hasLocalLinkage() || isa(GV)) return ResNode; - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); - return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); } assert(0 && "Dont know how to handle GlobalAddress"); @@ -511,6 +513,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue ResNode; SDValue HiPart; + DebugLoc dl = Op.getDebugLoc(); MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); @@ -519,12 +522,12 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); SDValue Ops[] = { JTI }; - HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); + HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1); } else // Emit Load from Global Pointer - HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0); + HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0); - SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); - ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI); + ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); return ResNode; } @@ -586,6 +589,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) SDValue Callee = TheCall->getCallee(); bool isVarArg = TheCall->isVarArg(); unsigned CC = TheCall->getCallingConv(); + DebugLoc dl = TheCall->getDebugLoc(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -627,13 +631,13 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) default: assert(0 && "Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: - Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::ZExt: - Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); break; case CCValAssign::AExt: - Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); break; } @@ -659,13 +663,13 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) // emit ISD::STORE whichs stores the // parameter value to a stack Location - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); } // Transform all store nodes into one single node because all store // nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -674,7 +678,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) // stuck together. SDValue InFlag; for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -706,7 +710,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) if (InFlag.getNode()) Ops.push_back(InFlag); - Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -736,9 +740,9 @@ LowerCALL(SDValue Op, SelectionDAG &DAG) // Reload GP value. FI = MipsFI->getGPFI(); SDValue FIN = DAG.getFrameIndex(FI,getPointerTy()); - SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); + SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0); Chain = GPLoad.getValue(1); - Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), + Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32), GPLoad, SDValue(0,0)); InFlag = Chain.getValue(1); } @@ -758,6 +762,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, unsigned CallingConv, SelectionDAG &DAG) { bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = TheCall->getDebugLoc(); // Assign locations to each value returned by this call. SmallVector RVLocs; @@ -768,7 +773,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { - Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), + Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); @@ -777,7 +782,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), &ResultVals[0], ResultVals.size()).getNode(); } @@ -796,6 +801,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); + DebugLoc dl = Op.getDebugLoc(); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); @@ -840,20 +846,20 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) // Transform the arguments stored on // physical registers into virtual ones unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); - SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); + SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted // to 32 bits. Insert an assert[sz]ext to capture this, then // truncate to the right size. if (VA.getLocInfo() == CCValAssign::SExt) - ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); else if (VA.getLocInfo() == CCValAssign::ZExt) - ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, + ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, DAG.getValueType(VA.getValVT())); if (VA.getLocInfo() != CCValAssign::Full) - ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); ArgValues.push_back(ArgValue); @@ -877,7 +883,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) // emit ISD::STORE whichs stores the // parameter value to a stack Location - ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); + ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0)); } } else { // VA.isRegLoc() @@ -900,7 +906,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); + ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0)); } } @@ -913,14 +919,14 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); MipsFI->setSRetReturnReg(Reg); } - SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]); + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); } ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e05a65ebf32..958b8ee1e94 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1140,11 +1140,12 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); SDValue Zero = DAG.getConstant(0, PtrVT); + DebugLoc dl = GSDN->getDebugLoc(); const TargetMachine &TM = DAG.getTarget(); - SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); - SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); + SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); + SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); // If this is a non-darwin platform, we don't support non-static relo models // yet. @@ -1152,23 +1153,23 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, !TM.getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to globals. // The address of the global is just (hi(&g)+lo(&g)). - return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); } if (TM.getRelocationModel() == Reloc::PIC_) { // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, PtrVT, + Hi = DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); } - Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); + Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); if (!TM.getSubtarget().hasLazyResolverStub(GV)) return Lo; // If the global is weak or external, we have to go through the lazy // resolution stub. - return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0); } SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { @@ -1270,6 +1271,7 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget) { + DebugLoc dl = Op.getNode()->getDebugLoc(); if (Subtarget.isMachoABI()) { // vastart just stores the address of the VarArgsFrameIndex slot into the @@ -1277,7 +1279,7 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); } // For ELF 32 ABI we follow the layout of the va_list struct. @@ -1326,26 +1328,26 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, const Value *SV = cast(Op.getOperand(2))->getValue(); // Store first byte : number of int regs - SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, + SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1), SV, 0); uint64_t nextOffset = FPROffset; - SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), + SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs SDValue secondStore = - DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); + DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset); nextOffset += StackOffset; - nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); + nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); // Store second word : arguments given on stack SDValue thirdStore = - DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); + DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset); nextOffset += FrameOffset; - nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); + nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); // Store third word : arguments given in registers - return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); + return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset); } @@ -1987,13 +1989,14 @@ static void StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVector &TailCallArgs, - SmallVector &MemOpChains) { + SmallVector &MemOpChains, + DebugLoc dl) { for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { SDValue Arg = TailCallArgs[i].Arg; SDValue FIN = TailCallArgs[i].FrameIdxOp; int FI = TailCallArgs[i].FrameIdx; // Store relative to framepointer. - MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, PseudoSourceValue::getFixedStack(FI), 0)); } @@ -2008,7 +2011,8 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue OldFP, int SPDiff, bool isPPC64, - bool isMachoABI) { + bool isMachoABI, + DebugLoc dl) { if (SPDiff) { // Calculate the new stack slot for the return address. int SlotSize = isPPC64 ? 8 : 4; @@ -2022,10 +2026,10 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); - Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, + Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewRetAddr), 0); SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); - Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx, + Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, PseudoSourceValue::getFixedStack(NewFPIdx), 0); } return Chain; @@ -2053,18 +2057,19 @@ CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, /// stack slot. Returns the chain as result and the loaded frame pointers in /// LROpOut/FPOpout. Used when tail calling. SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, - int SPDiff, - SDValue Chain, - SDValue &LROpOut, - SDValue &FPOpOut) { + int SPDiff, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut, + DebugLoc dl) { if (SPDiff) { // Load the LR and FP stack slot for later adjusting. MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); - LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); + LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0); Chain = SDValue(LROpOut.getNode(), 1); FPOpOut = getFramePointerFrameIndex(DAG); - FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0); + FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0); Chain = SDValue(FPOpOut.getNode(), 1); } return Chain; @@ -2092,7 +2097,8 @@ LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVector &MemOpChains, - SmallVector& TailCallArguments) { + SmallVector& TailCallArguments, + DebugLoc dl) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); if (!isTailCall) { if (isVector) { @@ -2101,10 +2107,10 @@ LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, StackPtr = DAG.getRegister(PPC::X1, MVT::i64); else StackPtr = DAG.getRegister(PPC::R1, MVT::i32); - PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, + PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, DAG.getConstant(ArgOffset, PtrVT)); } - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); // Calculate and remember argument location. } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, TailCallArguments); @@ -2165,7 +2171,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, // Load the return address and frame pointer so it can be move somewhere else // later. SDValue LROp, FPOp; - Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp); + Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl); // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument @@ -2306,7 +2312,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, } else { LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, false, MemOpChains, - TailCallArguments); + TailCallArguments, dl); inMem = true; } if (inMem || isMachoABI) { @@ -2356,7 +2362,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, } else { LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, false, MemOpChains, - TailCallArguments); + TailCallArguments, dl); inMem = true; } if (inMem || isMachoABI) { @@ -2417,7 +2423,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, // We are emitting Altivec params in order. LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, true, MemOpChains, - TailCallArguments); + TailCallArguments, dl); ArgOffset += 16; } break; @@ -2443,7 +2449,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, // We are emitting Altivec params in order. LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, isPPC64, isTailCall, true, MemOpChains, - TailCallArguments); + TailCallArguments, dl); ArgOffset += 16; } } @@ -2477,14 +2483,14 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, // Do not flag preceeding copytoreg stuff together with the following stuff. InFlag = SDValue(); StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, - MemOpChains2); + MemOpChains2, dl); if (!MemOpChains2.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains2[0], MemOpChains2.size()); // Store the return address to the appropriate stack slot. Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, - isPPC64, isMachoABI); + isPPC64, isMachoABI, dl); } // Emit callseq_end just before tailcall node. @@ -2679,6 +2685,7 @@ SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG, SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { // When we pop the dynamic allocation we need to restore the SP link. + DebugLoc dl = Op.getNode()->getDebugLoc(); // Get the corect type for pointers. MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -2693,13 +2700,13 @@ SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, SDValue SaveSP = Op.getOperand(1); // Load the old link SP. - SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); + SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0); // Restore the stack pointer. - Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); + Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); // Store the old link SP. - return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); + return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0); } @@ -2850,17 +2857,18 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { assert(Op.getOperand(0).getValueType().isFloatingPoint()); SDValue Src = Op.getOperand(0); + DebugLoc dl = Op.getNode()->getDebugLoc(); if (Src.getValueType() == MVT::f32) - Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); + Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); case MVT::i32: - Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); + Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src); break; case MVT::i64: - Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); + Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); break; } @@ -2868,26 +2876,29 @@ SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); // Emit a store to the stack slot. - SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); + SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0); // Result is a load from the stack slot. If loading 4 bytes, make sure to // add in a bias. if (Op.getValueType() == MVT::i32) - FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, + FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, DAG.getConstant(4, FIPtr.getValueType())); - return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0); } SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Don't handle ppc_fp128 here; let it be lowered to a libcall. if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) return SDValue(); if (Op.getOperand(0).getValueType() == MVT::i64) { - SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); + SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); + FP = DAG.getNode(ISD::FP_ROUND, dl, + MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } @@ -2902,26 +2913,27 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); - SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, + SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, Op.getOperand(0)); // STD the extended value into the stack slot. MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), MachineMemOperand::MOStore, 0, 8, 8); - SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other, + SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, DAG.getMemOperand(MO)); // Load the value as a double. - SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); + SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0); // FCFID it and return it. - SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); + FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); /* The rounding mode is in bits 30:31 of FPSR, and has the following settings: @@ -2950,36 +2962,36 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { // Save FP Control Word to register NodeTys.push_back(MVT::f64); // return register NodeTys.push_back(MVT::Flag); // unused in this context - SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); + SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); // Save FP register to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); - SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain, + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, StackSlot, NULL, 0); // Load FP Control Word from low 32 bits of stack slot. SDValue Four = DAG.getConstant(4, PtrVT); - SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); - SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); + SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); + SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0); // Transform as necessary SDValue CWD1 = - DAG.getNode(ISD::AND, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)); SDValue CWD2 = - DAG.getNode(ISD::SRL, MVT::i32, - DAG.getNode(ISD::AND, MVT::i32, - DAG.getNode(ISD::XOR, MVT::i32, + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD, DAG.getConstant(3, MVT::i32)), DAG.getConstant(3, MVT::i32)), DAG.getConstant(1, MVT::i32)); SDValue RetVal = - DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); return DAG.getNode((VT.getSizeInBits() < 16 ? - ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); + ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); } SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { @@ -3713,6 +3725,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); @@ -3720,10 +3733,10 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); // Store the input value into Value#0 of the stack slot. - SDValue Store = DAG.getStore(DAG.getEntryNode(), + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx, NULL, 0); // Load it out. - return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); + return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0); } SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { @@ -4893,6 +4906,7 @@ bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { } SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); // Depths > 0 not supported yet! if (cast(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); @@ -4906,7 +4920,8 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { // Make sure the function really does not optimize away the store of the RA // to the stack. FuncInfo->setLRStoreRequired(); - return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); + return DAG.getLoad(getPointerTy(), dl, + DAG.getEntryNode(), RetAddrFI, NULL, 0); } SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 56421df36f6..d6148b9dd18 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -340,10 +340,11 @@ namespace llvm { SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, - int SPDiff, - SDValue Chain, - SDValue &LROpOut, - SDValue &FPOpOut); + int SPDiff, + SDValue Chain, + SDValue &LROpOut, + SDValue &FPOpOut, + DebugLoc dl); SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 829ad07eaff..1ac49bd230f 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -231,6 +231,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { SDValue Chain = TheCall->getChain(); SDValue Callee = TheCall->getCallee(); bool isVarArg = TheCall->isVarArg(); + DebugLoc dl = TheCall->getDebugLoc(); #if 0 // Analyze operands of the call, assigning locations to each operand. @@ -344,7 +345,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { ValToStore = Val; } else { // Convert this to a FP value in an int reg. - Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); } break; @@ -358,14 +359,15 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { // Break into top and bottom parts by storing to the stack and loading // out the parts as integers. Top part goes in a reg. SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); - SDValue Store = DAG.getStore(DAG.getEntryNode(), Val, StackPtr, NULL, 0); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, + Val, StackPtr, NULL, 0); // Sparc is big-endian, so the high part comes first. - SDValue Hi = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0); + SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); // Increment the pointer to the other half. - StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, + StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4)); // Load the low part. - SDValue Lo = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0); + SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); @@ -386,9 +388,9 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { } // Split the value into top and bottom part. Top part goes in a reg. - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, DAG.getConstant(1, MVT::i32)); - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, DAG.getConstant(0, MVT::i32)); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); @@ -406,8 +408,9 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { if (ValToStore.getNode()) { SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); + PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore, + PtrOff, NULL, 0)); } ArgOffset += ObjSize; } @@ -415,7 +418,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { // Emit all stores, make sure the occur before any copies into physregs. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -429,7 +432,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { if (Reg >= SP::I0 && Reg <= SP::I7) Reg = Reg-SP::I0+SP::O0; - Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag); + Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -445,7 +448,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. SDValue Ops[] = { Chain, Callee, InFlag }; - Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2); + Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), @@ -467,7 +470,7 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { if (Reg >= SP::I0 && Reg <= SP::I7) Reg = Reg-SP::I0+SP::O0; - Chain = DAG.getCopyFromReg(Chain, Reg, + Chain = DAG.getCopyFromReg(Chain, dl, Reg, RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); @@ -476,7 +479,8 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], + return DAG.getNode(ISD::MERGE_VALUES, dl, + TheCall->getVTList(), &ResultVals[0], ResultVals.size()); } @@ -824,12 +828,13 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, SparcTargetLowering &TLI) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32, + DebugLoc dl = Op.getNode()->getDebugLoc(); + SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, DAG.getRegister(SP::I6, MVT::i32), DAG.getConstant(TLI.getVarArgsFrameOffset(), MVT::i32)); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0); } static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { @@ -838,28 +843,29 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { SDValue InChain = Node->getOperand(0); SDValue VAListPtr = Node->getOperand(1); const Value *SV = cast(Node->getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); + DebugLoc dl = Node->getDebugLoc(); + SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0); // Increment the pointer, VAList, to the next vaarg - SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, + SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, DAG.getConstant(VT.getSizeInBits()/8, MVT::i32)); // Store the incremented VAList to the legalized pointer - InChain = DAG.getStore(VAList.getValue(1), NextPtr, + InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, VAListPtr, SV, 0); // Load the actual argument out of the pointer VAList, unless this is an // f64 load. if (VT != MVT::f64) - return DAG.getLoad(VT, InChain, VAList, NULL, 0); + return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0); // Otherwise, load it as i64, then do a bitconvert. - SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); + SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0); // Bit-Convert the value to f64. SDValue Ops[2] = { - DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V), V.getValue(1) }; - return DAG.getMergeValues(Ops, 2); + return DAG.getMergeValues(Ops, 2, dl); } static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 5c964aa32af..b22d8a21a2f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4527,7 +4527,7 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { } SDValue -X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, +X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, int64_t Offset, SelectionDAG &DAG) const { bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; @@ -4546,8 +4546,8 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, // With PIC, the address is actually $g + Offset. if (IsPic && !Subtarget->isPICStyleRIPRel()) { - Result = DAG.getNode(ISD::ADD, getPointerTy(), - DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), + DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), Result); } @@ -4557,13 +4557,13 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, // the GV offset field. Platform check is inside GVRequiresExtraLoad() call // The same applies for external symbols during PIC codegen if (ExtraLoadRequired) - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, + Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, PseudoSourceValue::getGOT(), 0); // If there was a non-zero offset that we didn't fold, create an explicit // addition for it. if (Offset != 0) - Result = DAG.getNode(ISD::ADD, getPointerTy(), Result, + Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, DAG.getConstant(Offset, getPointerTy())); return Result; @@ -4573,7 +4573,7 @@ SDValue X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { const GlobalValue *GV = cast(Op)->getGlobal(); int64_t Offset = cast(Op)->getOffset(); - return LowerGlobalAddress(GV, Offset, DAG); + return LowerGlobalAddress(GV, Op.getNode()->getDebugLoc(), Offset, DAG); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit @@ -4653,6 +4653,7 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, // "local exec" model. static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const MVT PtrVT) { + DebugLoc dl = GA->getDebugLoc(); // Get the Thread Pointer SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial @@ -4663,12 +4664,12 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); if (GA->getGlobal()->isDeclaration()) // initial exec TLS model - Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, + Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, PseudoSourceValue::getGOT(), 0); // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. - return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); + return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); } SDValue @@ -8227,7 +8228,8 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, if (GA) { if (hasMemory) - Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG); + Op = LowerGlobalAddress(GA->getGlobal(), Op.getNode()->getDebugLoc(), + Offset, DAG); else Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), Offset); diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index cb6640809b8..214e59c7977 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -566,8 +566,8 @@ namespace llvm { SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); - SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset, - SelectionDAG &DAG) const; + SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, + int64_t Offset, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 82595bcc86e..75cb085599a 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -340,30 +340,32 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG) assert(0 && "unimplemented"); // FIX Arguments passed by reference need a extra dereference. SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); const Value *V = cast(Node->getOperand(2))->getValue(); MVT VT = Node->getValueType(0); - SDValue VAList = DAG.getLoad(getPointerTy(), Node->getOperand(0), + SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), Node->getOperand(1), V, 0); // Increment the pointer, VAList, to the next vararg - SDValue Tmp3 = DAG.getNode(ISD::ADD, getPointerTy(), VAList, + SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits(), getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Node->getOperand(1), V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0); // Load the actual argument out of the pointer VAList - return DAG.getLoad(VT, Tmp3, VAList, NULL, 0); + return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); } SDValue XCoreTargetLowering:: LowerVASTART(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // vastart stores the address of the VarArgsFrameIndex slot into the // memory location argument MachineFunction &MF = DAG.getMachineFunction(); XCoreFunctionInfo *XFI = MF.getInfo(); SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); const Value *SV = cast(Op.getOperand(2))->getValue(); - return DAG.getStore(Op.getOperand(0), Addr, Op.getOperand(1), SV, 0); + return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0); } SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { @@ -601,6 +603,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) SDValue Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0; unsigned CC = MF.getFunction()->getCallingConv(); + DebugLoc dl = Op.getDebugLoc(); // Assign locations to all of the incoming arguments. SmallVector ArgLocs; @@ -631,7 +634,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); - ArgValues.push_back(DAG.getCopyFromReg(Root, VReg, RegVT)); + ArgValues.push_back(DAG.getCopyFromReg(Root, dl, VReg, RegVT)); } } else { // sanity check @@ -650,7 +653,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) // Create the SelectionDAG nodes corresponding to a load //from this parameter SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); - ArgValues.push_back(DAG.getLoad(VA.getLocVT(), Root, FIN, NULL, 0)); + ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN, NULL, 0)); } } @@ -679,13 +682,13 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); RegInfo.addLiveIn(ArgRegs[i], VReg); - SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); // Move argument from virt reg -> stack - SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); } else { // This will point to the next argument passed via stack. @@ -699,7 +702,8 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG) // Return the new list of results. std::vector RetVT(Op.getNode()->value_begin(), Op.getNode()->value_end()); - return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); + return DAG.getNode(ISD::MERGE_VALUES, dl, RetVT, + &ArgValues[0], ArgValues.size()); } //===----------------------------------------------------------------------===//