From: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Date: Thu, 4 Feb 2016 18:45:25 +0000 (-0800)
Subject: UPSTREAM: irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
X-Git-Tag: firefly_0821_release~2520
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=33e9c6427c666f790d6c0a0c8451b856ce60d75c;p=firefly-linux-kernel-4.4.55.git

UPSTREAM: irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor

The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:

	4.1.1 Physical CPU Interface:
	The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
	on the state of a returned INTID are not guaranteed
	to be visible until after the execution of a DSB.

Not having this could result in missed interrupts, so let's add the
required barrier.

[Marc: fixed commit message]

Change-Id: I45f64990252b17a9e89ef69f3e53261b6af62ced
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596)
---

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 2731d3b25ed2..8ec88e5b290f 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
 	u64 irqstat;
 
 	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
+	dsb(sy);
 	return irqstat;
 }