From: Chris Fries Date: Wed, 13 Oct 2010 03:00:25 +0000 (-0500) Subject: [ARM] tegra_i2s_audio: add support for DSP (PCM) mode. X-Git-Tag: firefly_0821_release~9833^2~153^2~5 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=34179ead6cee2d0761132d330295802b1d6d863b;p=firefly-linux-kernel-4.4.55.git [ARM] tegra_i2s_audio: add support for DSP (PCM) mode. Change-Id: I132b8b7709c154ca1fb52f437966bd90451e89f7 Signed-off-by: Iliyan Malchev --- diff --git a/arch/arm/mach-tegra/include/mach/i2s.h b/arch/arm/mach-tegra/include/mach/i2s.h index 4801cec44999..ed8bc14c4ca4 100644 --- a/arch/arm/mach-tegra/include/mach/i2s.h +++ b/arch/arm/mach-tegra/include/mach/i2s.h @@ -160,5 +160,108 @@ (I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) #define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS \ (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT) +/* + * I2S_I2S_PCM_CTRL_0 + */ +#define I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ 0 +#define I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ 1 +#define I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ 2 +#define I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ 3 +#define I2S_PCM_TRM_EDGE_CTRL_SHIFT 9 + +#define I2S_I2S_PCM_TRM_EDGE_CTRL_MASK \ + (3 << I2S_I2S_PCM_TRM_EDGE_CTRL_SHIFT) +#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ \ + (I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ \ + << I2S_PCM_TRM_EDGE_CTRL_SHIFT) +#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ \ + (I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ \ + << I2S_PCM_TRM_EDGE_CTRL_SHIFT) +#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ \ + (I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ \ + << I2S_PCM_TRM_EDGE_CTRL_SHIFT) +#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ \ + (I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ \ + << I2S_PCM_TRM_EDGE_CTRL_SHIFT) + +#define I2S_PCM_TRM_MASK_BITS_ZERO 0 +#define I2S_PCM_TRM_MASK_BITS_ONE 1 +#define I2S_PCM_TRM_MASK_BITS_TWO 2 +#define I2S_PCM_TRM_MASK_BITS_THREE 3 +#define I2S_PCM_TRM_MASK_BITS_FOUR 4 +#define I2S_PCM_TRM_MASK_BITS_FIVE 5 +#define I2S_PCM_TRM_MASK_BITS_SIX 6 +#define I2S_PCM_TRM_MASK_BITS_SEVEN 7 +#define I2S_PCM_TRM_MASK_BITS_SHIFT 6 + +#define I2S_I2S_PCM_TRM_MASK_BITS_MASK \ + (7 << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_ZERO \ + (I2S_PCM_TRM_MASK_BITS_ZERO \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_ONE \ + (I2S_PCM_TRM_MASK_BITS_ONE \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_TWO \ + (I2S_PCM_TRM_MASK_BITS_TWO \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_THREE \ + (I2S_PCM_TRM_MASK_BITS_THREE \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_FOUR \ + (I2S_PCM_TRM_MASK_BITS_FOUR \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_FIVE \ + (I2S_PCM_TRM_MASK_BITS_FIVE \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_SIX \ + (I2S_PCM_TRM_MASK_BITS_SIX \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_TRM_MASK_BITS_SEVEN \ + (I2S_PCM_TRM_MASK_BITS_SEVEN \ + << I2S_PCM_TRM_MASK_BITS_SHIFT) + +#define I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL (1<<5) +#define I2S_I2S_PCM_CTRL_TRM_MODE (1<<4) + +#define I2S_PCM_RCV_MASK_BITS_ZERO 0 +#define I2S_PCM_RCV_MASK_BITS_ONE 1 +#define I2S_PCM_RCV_MASK_BITS_TWO 2 +#define I2S_PCM_RCV_MASK_BITS_THREE 3 +#define I2S_PCM_RCV_MASK_BITS_FOUR 4 +#define I2S_PCM_RCV_MASK_BITS_FIVE 5 +#define I2S_PCM_RCV_MASK_BITS_SIX 6 +#define I2S_PCM_RCV_MASK_BITS_SEVEN 7 +#define I2S_PCM_RCV_MASK_BITS_SHIFT 1 + +#define I2S_I2S_PCM_RCV_MASK_BITS_MASK \ + (7 << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_ZERO \ + (I2S_PCM_RCV_MASK_BITS_ZERO \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_ONE \ + (I2S_PCM_RCV_MASK_BITS_ONE \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_TWO \ + (I2S_PCM_RCV_MASK_BITS_TWO \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_THREE \ + (I2S_PCM_RCV_MASK_BITS_THREE \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_FOUR \ + (I2S_PCM_RCV_MASK_BITS_FOUR \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_FIVE \ + (I2S_PCM_RCV_MASK_BITS_FIVE \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_SIX \ + (I2S_PCM_RCV_MASK_BITS_SIX \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) +#define I2S_I2S_PCM_RCV_MASK_BITS_SEVEN \ + (I2S_PCM_RCV_MASK_BITS_SEVEN \ + << I2S_PCM_RCV_MASK_BITS_SHIFT) + +#define I2S_I2S_PCM_CTRL_RCV_MODE (1<<0) + #endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */ diff --git a/arch/arm/mach-tegra/tegra_i2s_audio.c b/arch/arm/mach-tegra/tegra_i2s_audio.c index 19a7796e55b8..64ba1be2ab1f 100644 --- a/arch/arm/mach-tegra/tegra_i2s_audio.c +++ b/arch/arm/mach-tegra/tegra_i2s_audio.c @@ -377,8 +377,14 @@ static int i2s_set_bit_format(unsigned long base, unsigned fmt) val = i2s_readl(base, I2S_I2S_CTRL_0); val &= ~I2S_I2S_CTRL_BIT_FORMAT_MASK; val |= fmt << I2S_BIT_FORMAT_SHIFT; - i2s_writel(base, val, I2S_I2S_CTRL_0); + + if (fmt == I2S_BIT_FORMAT_DSP) { + val = i2s_readl(base, I2S_I2S_PCM_CTRL_0); + val |= I2S_I2S_PCM_CTRL_TRM_MODE|I2S_I2S_PCM_CTRL_RCV_MODE; + i2s_writel(base, val, I2S_I2S_PCM_CTRL_0); + } + return 0; }