From: chenxing <chenxing@rock-chips.com>
Date: Mon, 13 May 2013 02:20:14 +0000 (+0800)
Subject: rk: add pll wait lock error dump infomations
X-Git-Tag: firefly_0821_release~7106
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=36320a82b3dbc761dc4b59ce77e502afc380fd35;p=firefly-linux-kernel-4.4.55.git

rk: add pll wait lock error dump infomations
---

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 66a2006b6957..fe79f20bb069 100644
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -615,6 +615,12 @@ static void pll_wait_lock(int pll_idx)
 		delay--;
 	}
 	if (delay == 0) {
+		CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
+				cru_readl(PLL_CONS(pll_idx, 0)),
+				cru_readl(PLL_CONS(pll_idx, 1)),
+				cru_readl(PLL_CONS(pll_idx, 2)),
+				cru_readl(PLL_CONS(pll_idx, 3)));
+
 		CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 		while(1);
 	}
diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c
index 5643b48e27ab..6e41a410804e 100644
--- a/arch/arm/mach-rk30/clock_data.c
+++ b/arch/arm/mach-rk30/clock_data.c
@@ -559,6 +559,12 @@ static void pll_wait_lock(int pll_idx)
 		delay--;
 	}
 	if (delay == 0) {
+		CRU_PRINTK_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
+				cru_readl(PLL_CONS(pll_idx, 0)),
+				cru_readl(PLL_CONS(pll_idx, 1)),
+				cru_readl(PLL_CONS(pll_idx, 2)),
+				cru_readl(PLL_CONS(pll_idx, 3)));
+
 		CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 		while(1);
 	}
diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index 5159dd55b1b3..cbfbd433bd9b 100755
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -614,6 +614,12 @@ static void pll_wait_lock(int pll_idx)
 		delay--;
 	}
 	if (delay == 0) {
+		CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
+				cru_readl(PLL_CONS(pll_idx, 0)),
+				cru_readl(PLL_CONS(pll_idx, 1)),
+				cru_readl(PLL_CONS(pll_idx, 2)),
+				cru_readl(PLL_CONS(pll_idx, 3)));
+
 		CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 		while(1);
 	}