From: Craig Topper <craig.topper@gmail.com>
Date: Wed, 15 Jan 2014 05:02:02 +0000 (+0000)
Subject: Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=38e6f7301d2306230d5eb200ecdab2b365079096;p=oota-llvm.git

Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199295 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 17fd0ec5c6e..986fd8b8f3d 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -232,6 +232,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   Form     = byteFromRec(Rec, "FormBits");
 
   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
+  HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
@@ -254,10 +255,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
 
   Operands = &insn.Operands.OperandList;
 
-  IsSSE            = ((HasOpSizePrefix || Prefix == X86Local::PD ||
-                       Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
-                      (Name.find("16") == Name.npos)) ||
-                     (Name.find("CRC32") != Name.npos);
   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
 
   // Check for 64-bit inst which does not require REX
@@ -558,9 +555,9 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
                                                               HasOpSizePrefix);
   Spec->operands[operandIndex].type = typeFromString(typeName,
-                                                     IsSSE,
                                                      HasREX_WPrefix,
-                                                     HasOpSizePrefix);
+                                                     HasOpSizePrefix,
+                                                     HasOpSize16Prefix);
 
   ++operandIndex;
   ++physicalOperandIndex;
@@ -1164,36 +1161,34 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
 
 #define TYPE(str, type) if (s == str) return type;
 OperandType RecognizableInstr::typeFromString(const std::string &s,
-                                              bool isSSE,
                                               bool hasREX_WPrefix,
-                                              bool hasOpSizePrefix) {
-  if (isSSE) {
-    // For SSE instructions, we ignore the OpSize prefix and force operand
-    // sizes.
-    TYPE("GR16",              TYPE_R16)
-    TYPE("GR32",              TYPE_R32)
-    TYPE("GR64",              TYPE_R64)
-  }
+                                              bool hasOpSizePrefix,
+                                              bool hasOpSize16Prefix) {
   if(hasREX_WPrefix) {
     // For instructions with a REX_W prefix, a declared 32-bit register encoding
     // is special.
     TYPE("GR32",              TYPE_R32)
   }
-  if(!hasOpSizePrefix) {
-    // For instructions without an OpSize prefix, a declared 16-bit register or
+  if(hasOpSizePrefix) {
+    // For instructions with an OpSize prefix, a declared 16-bit register or
+    // immediate encoding is special.
+    TYPE("GR16",              TYPE_Rv)
+    TYPE("i16imm",            TYPE_IMMv)
+  }
+  if(hasOpSize16Prefix) {
+    // For instructions with an OpSize16 prefix, a declared 32-bit register or
     // immediate encoding is special.
-    TYPE("GR16",              TYPE_R16)
-    TYPE("i16imm",            TYPE_IMM16)
+    TYPE("GR32",              TYPE_Rv)
   }
   TYPE("i16mem",              TYPE_Mv)
-  TYPE("i16imm",              TYPE_IMMv)
+  TYPE("i16imm",              TYPE_IMM16)
   TYPE("i16i8imm",            TYPE_IMMv)
-  TYPE("GR16",                TYPE_Rv)
+  TYPE("GR16",                TYPE_R16)
   TYPE("i32mem",              TYPE_Mv)
   TYPE("i32imm",              TYPE_IMMv)
   TYPE("i32i8imm",            TYPE_IMM32)
   TYPE("u32u8imm",            TYPE_IMM32)
-  TYPE("GR32",                TYPE_Rv)
+  TYPE("GR32",                TYPE_R32)
   TYPE("GR32orGR64",          TYPE_R32)
   TYPE("i64mem",              TYPE_Mv)
   TYPE("i64i32imm",           TYPE_IMM64)
diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index ef3bdfee254..08e984e9509 100644
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -46,6 +46,8 @@ private:
   uint8_t Form;
   /// The hasOpSizePrefix field from the record
   bool HasOpSizePrefix;
+  /// The hasOpSize16Prefix field from the record
+  bool HasOpSize16Prefix;
   /// The hasAdSizePrefix field from the record
   bool HasAdSizePrefix;
   /// The hasREX_WPrefix field from the record
@@ -89,9 +91,7 @@ private:
   std::string Name;
   /// The AT&T AsmString for the instruction
   std::string AsmString;
-  
-  /// Indicates whether the instruction is SSE
-  bool IsSSE;
+
   /// Indicates whether the instruction should be emitted into the decode
   /// tables; regardless, it will be emitted into the instruction info table
   bool ShouldBeEmitted;