From: Chris Lattner <sabre@nondot.org>
Date: Thu, 12 Apr 2007 06:00:20 +0000 (+0000)
Subject: the result of an inline asm copy can be an arbitrary VT that the register
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3a508c94a6c6f124e8b0549358ce76deb92ab662;p=oota-llvm.git

the result of an inline asm copy can be an arbitrary VT that the register
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 77374f63c84..c4add16c744 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3055,9 +3055,10 @@ GetRegistersForValue(const std::string &ConstrCode,
     // how to maintain the constraint.  If it isn't, go ahead and create vreg
     // and let the regalloc do the right thing.
     if (!isOutReg || !isInReg) {
-      if (VT == MVT::Other)
-        ValueVT = *PhysReg.second->vt_begin();
       RegVT = *PhysReg.second->vt_begin();
+      
+      if (VT == MVT::Other)
+        ValueVT = RegVT;
 
       // Create the appropriate number of virtual registers.
       SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
@@ -3459,8 +3460,24 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
 
   // If this asm returns a register value, copy the result from that register
   // and set it as the value of the call.
-  if (!RetValRegs.Regs.empty())
-    setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
+  if (!RetValRegs.Regs.empty()) {
+    SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag);
+    
+    // If the result of the inline asm is a vector, it may have the wrong
+    // width/num elts.  Make sure to convert it to the right type with
+    // vbit_convert.
+    if (Val.getValueType() == MVT::Vector) {
+      const VectorType *VTy = cast<VectorType>(I.getType());
+      unsigned DesiredNumElts = VTy->getNumElements();
+      MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType());
+      
+      Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 
+                        DAG.getConstant(DesiredNumElts, MVT::i32),
+                        DAG.getValueType(DesiredEltVT));
+    }
+    
+    setValue(&I, Val);
+  }
   
   std::vector<std::pair<SDOperand, Value*> > StoresToEmit;