From: Colin LeMahieu Date: Mon, 29 Dec 2014 20:00:43 +0000 (+0000) Subject: [Hexagon] Replacing the remaining postincrement stores with versions that have encodi... X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3dc54ee5a48340cd46e1ac04c151ff7fb342fec0;p=oota-llvm.git [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 9bf2be9e100..374f625e966 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -709,9 +709,9 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) { unsigned Opcode = 0; // Figure out the post inc version of opcode. - if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri; - else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri; - else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri; + if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi; + else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi; + else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi; else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi; else llvm_unreachable("unknown memory type"); diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 4d52d7732c0..cc1665515ff 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1437,8 +1437,8 @@ isConditionalStore (const MachineInstr* MI) const { case Hexagon::STrid_indexed_cPt : case Hexagon::STrid_indexed_cNotPt : case Hexagon::STrid_indexed_shl_cPt_V4 : - case Hexagon::POST_STdri_cPt : - case Hexagon::POST_STdri_cNotPt : + case Hexagon::S2_pstorerdt_pi: + case Hexagon::S2_pstorerdf_pi: case Hexagon::STrih_cPt : case Hexagon::STrih_cNotPt : case Hexagon::STrih_indexed_cPt : @@ -1447,8 +1447,8 @@ isConditionalStore (const MachineInstr* MI) const { case Hexagon::STrih_imm_cNotPt_V4 : case Hexagon::STrih_indexed_shl_cPt_V4 : case Hexagon::STrih_indexed_shl_cNotPt_V4 : - case Hexagon::POST_SThri_cPt : - case Hexagon::POST_SThri_cNotPt : + case Hexagon::S2_pstorerht_pi: + case Hexagon::S2_pstorerhf_pi: case Hexagon::STriw_cPt : case Hexagon::STriw_cNotPt : case Hexagon::STriw_indexed_cPt : @@ -1457,8 +1457,8 @@ isConditionalStore (const MachineInstr* MI) const { case Hexagon::STriw_imm_cNotPt_V4 : case Hexagon::STriw_indexed_shl_cPt_V4 : case Hexagon::STriw_indexed_shl_cNotPt_V4 : - case Hexagon::POST_STwri_cPt : - case Hexagon::POST_STwri_cNotPt : + case Hexagon::S2_pstorerit_pi: + case Hexagon::S2_pstorerif_pi: return QRI.Subtarget.hasV4TOps(); // V4 global address store before promoting to dot new. diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index aac3aa8b859..f85f933c36f 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2753,55 +2753,17 @@ multiclass ST_PostInc; -//===----------------------------------------------------------------------===// -// Post increment store -//===----------------------------------------------------------------------===// - -multiclass ST_PostInc_Pbase { - let isPredicatedNew = isPredNew in - def NAME : STInst2PI<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2++#$offset) = $src3", - [], - "$src2 = $dst">; -} +let accessSize = HalfWordAccess, isCodeGenOnly = 0 in +defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>; -multiclass ST_PostInc_Pred { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_PostInc_Pbase; - // Predicate new - let Predicates = [HasV4T], validSubTargets = HasV4SubT in - defm _cdn#NAME#_V4 : ST_PostInc_Pbase; - } -} - -let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in -multiclass ST_PostInc2 { - - let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in { - let isPredicable = 1 in - def NAME : STInst2PI<(outs IntRegs:$dst), - (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), - mnemonic#"($src1++#$offset) = $src2", - [], - "$src1 = $dst">; - - let isPredicated = 1 in { - defm Pt : ST_PostInc_Pred; - defm NotPt : ST_PostInc_Pred; - } - } -} +let accessSize = WordAccess, isCodeGenOnly = 0 in +defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>; -defm POST_SThri: ST_PostInc2 <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel; -defm POST_STwri: ST_PostInc2 <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel; +let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in +defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>; -let isNVStorable = 0 in -defm POST_STdri: ST_PostInc2 <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel; +let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in +defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>; def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2, s4_3ImmPred:$offset), @@ -2809,14 +2771,14 @@ def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2, def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2, s4_3ImmPred:$offset), - (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>; + (S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>; def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset), - (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>; + (S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>; def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2, s4_3ImmPred:$offset), - (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>; + (S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>; //===----------------------------------------------------------------------===// // multiclass for the store instructions with MEMri operand. diff --git a/test/MC/Disassembler/Hexagon/st.txt b/test/MC/Disassembler/Hexagon/st.txt index 1b48e6709bb..b098aed82ee 100644 --- a/test/MC/Disassembler/Hexagon/st.txt +++ b/test/MC/Disassembler/Hexagon/st.txt @@ -1,5 +1,18 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0x28 0xd4 0xd1 0xab +# CHECK: memd(r17++#40) = r21:20 +0x2b 0xf4 0xd1 0xab +# CHECK: if (p3) memd(r17++#40) = r21:20 +0x2f 0xf4 0xd1 0xab +# CHECK: if (!p3) memd(r17++#40) = r21:20 +0x03 0x40 0x45 0x85 0xab 0xf4 0xd1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memd(r17++#40) = r21:20 +0x03 0x40 0x45 0x85 0xaf 0xf4 0xd1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20 + 0x28 0xd5 0x11 0xab # CHECK: memb(r17++#5) = r21 0x2b 0xf5 0x11 0xab @@ -11,4 +24,30 @@ # CHECK-NEXT: if (p3.new) memb(r17++#5) = r21 0x03 0x40 0x45 0x85 0xaf 0xf5 0x11 0xab # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21 \ No newline at end of file +# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21 + +0x28 0xd5 0x51 0xab +# CHECK: memh(r17++#10) = r21 +0x2b 0xf5 0x51 0xab +# CHECK: if (p3) memh(r17++#10) = r21 +0x2f 0xf5 0x51 0xab +# CHECK: if (!p3) memh(r17++#10) = r21 +0x03 0x40 0x45 0x85 0xab 0xf5 0x51 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memh(r17++#10) = r21 +0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21 + +0x28 0xd5 0x91 0xab +# CHECK: memw(r17++#20) = r21 +0x2b 0xf5 0x91 0xab +# CHECK: if (p3) memw(r17++#20) = r21 +0x2f 0xf5 0x91 0xab +# CHECK: if (!p3) memw(r17++#20) = r21 +0x03 0x40 0x45 0x85 0xaf 0xf5 0x91 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r21 +0x03 0x40 0x45 0x85 0xab 0xf5 0x91 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) memw(r17++#20) = r21 \ No newline at end of file