From: Chris Lattner <sabre@nondot.org>
Date: Fri, 12 Aug 2005 23:54:58 +0000 (+0000)
Subject: implement a couple of simple shift foldings.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3e27b1f5c4bbbc5729a154b9b76b4231bb0ad9b9;p=oota-llvm.git

implement a couple of simple shift foldings.

e.g.  (X & 7) >> 3   -> 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22774 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 12482efd708..342148adb4a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -993,6 +993,24 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
         return getNode(ISD::UNDEF, N1.getValueType());
       }
       if (C2 == 0) return N1;
+      
+      if (Opcode == ISD::SRA) {
+        // If the sign bit is known to be zero, switch this to a SRL.
+        if (MaskedValueIsZero(N1,
+                              1ULL << MVT::getSizeInBits(N1.getValueType())-1,
+                              TLI))
+          return getNode(ISD::SRL, N1.getValueType(), N1, N2);
+      } else {
+        // If the part left over is known to be zero, the whole thing is zero.
+        uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType()));
+        if (Opcode == ISD::SRL) {
+          if (MaskedValueIsZero(N1, TypeMask << C2, TLI))
+            return getConstant(0, N1.getValueType());
+        } else if (Opcode == ISD::SHL) {
+          if (MaskedValueIsZero(N1, TypeMask >> C2, TLI))
+            return getConstant(0, N1.getValueType());
+        }
+      }
 
       if (Opcode == ISD::SHL && N1.getNumOperands() == 2)
         if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {