From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 25 Jan 2006 09:12:57 +0000 (+0000)
Subject: If scheduler choice is the default (-sched=default), use target scheduling
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3f23952404cd03a8ab934cedcef7916f52a796c0;p=oota-llvm.git

If scheduler choice is the default (-sched=default), use target scheduling
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25599 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7badd283a82..06a3b016de2 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -59,8 +59,10 @@ namespace {
   ISHeuristic(
     "sched",
     cl::desc("Choose scheduling style"),
-    cl::init(noScheduling),
+    cl::init(defaultScheduling),
     cl::values(
+      clEnumValN(defaultScheduling, "default",
+                 "Target preferred scheduling style"),
       clEnumValN(noScheduling, "none",
                  "No scheduling: breadth first sequencing"),
       clEnumValN(simpleScheduling, "simple",
@@ -69,7 +71,7 @@ namespace {
       clEnumValN(simpleNoItinScheduling, "simple-noitin",
                  "Simple two pass scheduling: Same as simple "
                  "except using generic latency"),
-      clEnumValN(listSchedulingBURR, "list-BURR",
+      clEnumValN(listSchedulingBURR, "list-burr",
                  "Bottom up register reduction list scheduling"),
       clEnumValEnd));
 } // namespace
@@ -1772,6 +1774,12 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
 
   switch (ISHeuristic) {
   default: assert(0 && "Unrecognized scheduling heuristic");
+  case defaultScheduling:
+    if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
+      SL = createSimpleDAGScheduler(noScheduling, DAG, BB);
+    else /* TargetLowering::SchedulingForRegPressure */
+      SL = createBURRListDAGScheduler(DAG, BB);
+    break;
   case noScheduling:
   case simpleScheduling:
   case simpleNoItinScheduling: