From: Alex Lorenz <arphaman@gmail.com>
Date: Tue, 18 Aug 2015 17:17:13 +0000 (+0000)
Subject: MIR Parser: Implicit register verifier should accept unexpected implicit
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=3f6954d463fcb6a2403f0a6b2358f50321ae5c59;p=oota-llvm.git

MIR Parser: Implicit register verifier should accept unexpected implicit
subregister operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245315 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/MIRParser/MIParser.cpp b/lib/CodeGen/MIRParser/MIParser.cpp
index c11117312c9..c6c0e4516f1 100644
--- a/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/lib/CodeGen/MIRParser/MIParser.cpp
@@ -695,6 +695,19 @@ bool MIParser::verifyImplicitOperands(
       if (ImplicitOperand.isIdenticalTo(Operand))
         continue;
       if (Operand.isReg() && Operand.isImplicit()) {
+        // Check if this implicit register is a subregister of an explicit
+        // register operand.
+        bool IsImplicitSubRegister = false;
+        for (size_t K = 0, E = Operands.size(); K < E; ++K) {
+          const auto &Op = Operands[K].Operand;
+          if (Op.isReg() && !Op.isImplicit() &&
+              TRI->isSubRegister(Op.getReg(), Operand.getReg())) {
+            IsImplicitSubRegister = true;
+            break;
+          }
+        }
+        if (IsImplicitSubRegister)
+          continue;
         return error(Operands[J].Begin,
                      Twine("expected an implicit register operand '") +
                          printImplicitRegisterFlag(ImplicitOperand) + " %" +
diff --git a/test/CodeGen/MIR/X86/implicit-register-flag.mir b/test/CodeGen/MIR/X86/implicit-register-flag.mir
index a18a578e249..b0a15ed93a8 100644
--- a/test/CodeGen/MIR/X86/implicit-register-flag.mir
+++ b/test/CodeGen/MIR/X86/implicit-register-flag.mir
@@ -16,6 +16,16 @@
     ret i32 %a
   }
 
+  define i1 @implicit_subregister1() {
+  entry:
+    ret i1 false
+  }
+
+  define i16 @implicit_subregister2() {
+  entry:
+    ret i16 0
+  }
+
 ...
 ---
 name:            foo
@@ -36,3 +46,23 @@ body: |
     %eax = COPY %edi
     RETQ %eax
 ...
+---
+name:            implicit_subregister1
+body: |
+  bb.0.entry:
+  ; Verify that the implicit register verifier won't report an error on implicit
+  ; subregisters.
+  ; CHECK-LABEL: name: implicit_subregister1
+  ; CHECK: dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
+    dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
+    RETQ killed %al
+...
+---
+name:            implicit_subregister2
+body: |
+  bb.0.entry:
+  ; CHECK-LABEL: name: implicit_subregister2
+  ; CHECK: dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w
+    dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w
+    RETQ killed %r15w
+...