From: Michael Liao <michael.liao@intel.com>
Date: Wed, 17 Oct 2012 22:41:15 +0000 (+0000)
Subject: Revert r166049
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4031e9018b071d25e5fc905aa38a943fcd9facb6;p=oota-llvm.git

Revert r166049

- In general, it's unsafe for this transformation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166135 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4ac6d1b5163..0c5cd3e6cab 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5308,52 +5308,6 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
     if (Reduced.getNode())
       return Reduced;
   }
-  // fold (trunc (fptoXi x)) -> (smaller fptoXi x)
-  if ((N0.getOpcode() == ISD::FP_TO_UINT ||
-       N0.getOpcode() == ISD::FP_TO_SINT) && !LegalTypes)
-    return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
-  // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
-  // where ... are all 'undef'.
-  if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
-    SmallVector<EVT, 8> VTs;
-    SDValue V;
-    unsigned Idx = 0;
-    unsigned NumDefs = 0;
-
-    for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
-      SDValue X = N0.getOperand(i);
-      if (X.getOpcode() != ISD::UNDEF) {
-        V = X;
-        Idx = i;
-        NumDefs++;
-      }
-      // Stop if more than one members are non-undef.
-      if (NumDefs > 1)
-        break;
-      VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
-                                     VT.getVectorElementType(),
-                                     X.getValueType().getVectorNumElements()));
-    }
-
-    if (NumDefs == 0)
-      return DAG.getUNDEF(VT);
-
-    if (NumDefs == 1) {
-      assert(V.getNode() && "The single defined operand is empty!");
-      SmallVector<SDValue, 8> Opnds;
-      for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
-        if (i != Idx) {
-          Opnds.push_back(DAG.getUNDEF(VTs[i]));
-          continue;
-        }
-        SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V);
-        AddToWorkList(NV.getNode());
-        Opnds.push_back(NV);
-      }
-      return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
-                         &Opnds[0], Opnds.size());
-    }
-  }
 
   // Simplify the operands using demanded-bits information.
   if (!VT.isVector() &&
diff --git a/test/CodeGen/X86/trunc-fp2int.ll b/test/CodeGen/X86/trunc-fp2int.ll
deleted file mode 100644
index 792af16c955..00000000000
--- a/test/CodeGen/X86/trunc-fp2int.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s
-
-define <4 x i8> @bar(<4 x float> %in) nounwind readnone alwaysinline {
-  %1 = fptoui <4 x float> %in to <4 x i8>
-  ret <4 x i8> %1
-; CHECK: bar
-; CHECK: cvttps2dq
-}
-define <4 x i8> @foo(<4 x float> %in) nounwind readnone alwaysinline {
-  %1 = fptoui <4 x float> %in to <4 x i32>
-  %2 = trunc <4 x i32> %1 to <4 x i16>
-  %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-  %4 = trunc <8 x i16> %3 to <8 x i8>
-  %5 = shufflevector <8 x i8> %4, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-  ret <4 x i8> %5
-; CHECK: foo
-; CHECK: cvttps2dq
-}