From: chenxing <chenxing@rock-chips.com>
Date: Wed, 29 Aug 2012 12:54:15 +0000 (+0800)
Subject: rk3066b: rename vepu/vdpu, ddr src gate add CLK_GATE_ACLK_CIF1 point to CLK_GATE_ACLK... 
X-Git-Tag: firefly_0821_release~8770
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=41fcedae3d8bb267b17570c2b5ca6537d6e6fb97;p=firefly-linux-kernel-4.4.55.git

rk3066b: rename vepu/vdpu, ddr src gate add CLK_GATE_ACLK_CIF1 point to CLK_GATE_ACLK_CIF0
---

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index fe80054276ce..675f1f6144eb 100644
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -1382,7 +1382,7 @@ static struct clk aclk_vepu = {
 	//.set_rate	= clksel_set_rate_freediv,
 	.set_rate	= clkset_rate_freediv_autosel_parents,
 	.clksel_con	= CRU_CLKSELS_CON(32),
-	.gate_idx	= CLK_GATE_ACLK_VEPU_SRC,
+	.gate_idx	= CLK_GATE_ACLK_VEPU,
 	CRU_DIV_SET(0x1f, 0, 32),
 	CRU_SRC_SET(0x1, 7),
 	CRU_PARENTS_SET(aclk_vepu_parents),
@@ -1397,7 +1397,7 @@ static struct clk aclk_vdpu = {
 	//.set_rate	= clksel_set_rate_freediv,
 	.set_rate	= clkset_rate_freediv_autosel_parents,
 	.clksel_con	= CRU_CLKSELS_CON(32),
-	.gate_idx	= CLK_GATE_ACLK_VDPU_SRC,
+	.gate_idx	= CLK_GATE_ACLK_VDPU,
 	CRU_DIV_SET(0x1f, 8, 32),
 	CRU_SRC_SET(0x1, 15),
 	CRU_PARENTS_SET(aclk_vdpu_parents),
diff --git a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
index caafa931d07d..328d21dfedc8 100755
--- a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
+++ b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
@@ -185,7 +185,7 @@ enum cru_clk_gate {
 	/* SCU CLK GATE 0 CON */
 	CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
 	CLK_GATE_CPU_GPLL_PATH,
-	CLK_GATE_DDRPHY_SRC,
+	CLK_GATE_DDRPHY,
 	CLK_GATE_ACLK_CPU,
 
 	CLK_GATE_HCLK_CPU,
@@ -254,9 +254,9 @@ enum cru_clk_gate {
 	CLK_GATE_CIF0_OUT,
 
 	CLK_GATE_3RES8,
-	CLK_GATE_ACLK_VEPU_SRC,
+	CLK_GATE_ACLK_VEPU,
 	CLK_GATE_HCLK_VEPU,
-	CLK_GATE_ACLK_VDPU_SRC,
+	CLK_GATE_ACLK_VDPU,
 
 	CLK_GATE_HCLK_VDPU,
 	CLK_GATE_3RES13,
@@ -385,7 +385,7 @@ enum cru_clk_gate {
 
 	CLK_GATE_MAX,
 };
-
+#define CLK_GATE_ACLK_CIF1 CLK_GATE_ACLK_CIF0
 #define SOFT_RST_ID(i)		(16 * (i))
 
 enum cru_soft_reset {