From: Jim Grosbach Date: Fri, 12 Oct 2012 22:59:21 +0000 (+0000) Subject: ARM: Mark VSELECT as 'expand'. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4346fa9437116bbdb10acddb982c230f46696737;p=oota-llvm.git ARM: Mark VSELECT as 'expand'. The backend already pattern matches to form VBSL when it can. We may want to teach it to use the vbsl intrinsics at some point to prevent machine licm from mucking with this, but using the Expand is completely correct. http://llvm.org/bugs/show_bug.cgi?id=13831 http://llvm.org/bugs/show_bug.cgi?id=13961 Patch by Peter Couperus . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165845 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 051aab05cbd..bd0c659414e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -122,6 +122,7 @@ void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); setOperationAction(ISD::SELECT, VT, Expand); setOperationAction(ISD::SELECT_CC, VT, Expand); + setOperationAction(ISD::VSELECT, VT, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); if (VT.isInteger()) { setOperationAction(ISD::SHL, VT, Custom); diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll new file mode 100644 index 00000000000..f5994046de4 --- /dev/null +++ b/test/CodeGen/ARM/vselect_imax.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; Make sure that ARM backend with NEON handles vselect. + +define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { +; CHECK: vcgt.s32 [[QR:q[0-9]+]], [[Q1:q[0-9]+]], [[Q2:q[0-9]+]] +; CHECK: vbsl [[QR]], [[Q1]], [[Q2]] + %cmpres = icmp sgt <4 x i32> %a, %b + %maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b + store <4 x i32> %maxres, <4 x i32>* %m + ret void +} +