From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 26 Oct 2015 21:24:09 +0000 (+0000)
Subject: reorganize logic; NFCI
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4414354c549a39cf71fcde87b830cca4de28af6f;p=oota-llvm.git

reorganize logic; NFCI

This is a preliminary step before adding another optimization
to PerformBITCASTCombine().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251349 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 63c2b9a21dc..49fd42c0629 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -23123,21 +23123,40 @@ static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
                      EltNo);
 }
 
-/// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
-/// special and don't usually play with other vector types, it's better to
-/// handle them early to be sure we emit efficient code by avoiding
-/// store-load conversions.
-static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
-  if (N->getValueType(0) != MVT::x86mmx ||
-      N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
-      N->getOperand(0)->getValueType(0) != MVT::v2i32)
-    return SDValue();
+static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
+                                     const X86Subtarget *Subtarget) {
+  SDValue N0 = N->getOperand(0);
+  EVT VT = N->getValueType(0);
 
-  SDValue V = N->getOperand(0);
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
-  if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
-    return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
-                       N->getValueType(0), V.getOperand(0));
+  // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
+  // special and don't usually play with other vector types, it's better to
+  // handle them early to be sure we emit efficient code by avoiding
+  // store-load conversions.
+  if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
+      N0.getValueType() == MVT::v2i32 &&
+      isa<ConstantSDNode>(N0.getOperand(1))) {
+    SDValue N00 = N0->getOperand(0);
+    if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
+      return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
+  }
+
+  if ((Subtarget->hasSSE1() && VT == MVT::f32) ||
+      (Subtarget->hasSSE2() && VT == MVT::f64)) {
+    if (N0.getOpcode() == ISD::AND) {
+      if (isa<ConstantSDNode>(N0.getOperand(1))) {
+        SDValue N00 = N0.getOperand(0);
+        if (N00.getOpcode() == ISD::BITCAST) {
+          SDValue N000 = N00.getOperand(0);
+          if (N00.getOperand(0).getValueType() == VT) {
+            unsigned FPOpcode = X86ISD::FAND;
+            SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
+            SDValue FPLogic = DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
+            return FPLogic;
+          }
+        }
+      }
+    }
+  }
 
   return SDValue();
 }