From: Brian Gaeke <gaeke@uiuc.edu>
Date: Sat, 11 Dec 2004 05:19:03 +0000 (+0000)
Subject: Look for many more moves to fold (previously, we only
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4658ba13a816f54f9a5e36fc6ae6456ed1b8e62d;p=oota-llvm.git

Look for many more moves to fold (previously, we only
*or g0, x      add g0, x          recognized * as a move)
 or  x, g0     add  x, g0
 or  0, x      add  0, x
 or  x, 0      add  x, 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18793 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 01c513ac5ed..6a60a66608a 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -21,16 +21,38 @@ SparcV8InstrInfo::SparcV8InstrInfo()
   : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
 }
 
+static bool isZeroImmed (const MachineOperand &op) {
+  return (op.isImmediate() && op.getImmedValue() == 0);
+}
+
 /// Return true if the instruction is a register to register move and
 /// leave the source and dest operands in the passed parameters.
 ///
 bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
                                    unsigned &SrcReg, unsigned &DstReg) const {
-  if (MI.getOpcode() == V8::ORrr) {
-    if (MI.getOperand(1).getReg() == V8::G0) {  // X = or G0, Y -> X = Y
+  // We look for 3 kinds of patterns here:
+  // or with G0 or 0
+  // add with G0 or 0
+  // fmovs or FpMOVD (pseudo double move).
+  if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
+    if (MI.getOperand(1).getReg() == V8::G0) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(2).getReg();
+      return true;
+    } else if (MI.getOperand (2).getReg() == V8::G0) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(1).getReg();
+      return true;
+    }
+  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
+    if (isZeroImmed (MI.getOperand (1))) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(2).getReg();
       return true;
+    } else if (isZeroImmed (MI.getOperand (2))) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(1).getReg();
+      return true;
     }
   } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
     SrcReg = MI.getOperand(1).getReg();
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.cpp b/lib/Target/SparcV8/SparcV8InstrInfo.cpp
index 01c513ac5ed..6a60a66608a 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.cpp
@@ -21,16 +21,38 @@ SparcV8InstrInfo::SparcV8InstrInfo()
   : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
 }
 
+static bool isZeroImmed (const MachineOperand &op) {
+  return (op.isImmediate() && op.getImmedValue() == 0);
+}
+
 /// Return true if the instruction is a register to register move and
 /// leave the source and dest operands in the passed parameters.
 ///
 bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
                                    unsigned &SrcReg, unsigned &DstReg) const {
-  if (MI.getOpcode() == V8::ORrr) {
-    if (MI.getOperand(1).getReg() == V8::G0) {  // X = or G0, Y -> X = Y
+  // We look for 3 kinds of patterns here:
+  // or with G0 or 0
+  // add with G0 or 0
+  // fmovs or FpMOVD (pseudo double move).
+  if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
+    if (MI.getOperand(1).getReg() == V8::G0) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(2).getReg();
+      return true;
+    } else if (MI.getOperand (2).getReg() == V8::G0) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(1).getReg();
+      return true;
+    }
+  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
+    if (isZeroImmed (MI.getOperand (1))) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(2).getReg();
       return true;
+    } else if (isZeroImmed (MI.getOperand (2))) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(1).getReg();
+      return true;
     }
   } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
     SrcReg = MI.getOperand(1).getReg();