From: Evan Cheng Date: Mon, 9 Oct 2006 20:57:25 +0000 (+0000) Subject: Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=466685d41a9ea4905b9486fea38e83802e46f196;p=oota-llvm.git Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f2b23d75169..96456aa5f05 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -221,7 +221,6 @@ namespace { SDOperand visitBRCOND(SDNode *N); SDOperand visitBR_CC(SDNode *N); SDOperand visitLOAD(SDNode *N); - SDOperand visitLOADX(SDNode *N); SDOperand visitSTORE(SDNode *N); SDOperand visitINSERT_VECTOR_ELT(SDNode *N); SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); @@ -499,7 +498,6 @@ SDOperand DAGCombiner::visit(SDNode *N) { case ISD::BRCOND: return visitBRCOND(N); case ISD::BR_CC: return visitBR_CC(N); case ISD::LOAD: return visitLOAD(N); - case ISD::LOADX: return visitLOADX(N); case ISD::STORE: return visitSTORE(N); case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); @@ -1078,14 +1076,15 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { return SDOperand(N, 0); // fold (zext_inreg (extload x)) -> (zextload x) if (ISD::isEXTLoad(N0.Val)) { - MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); + LoadSDNode *LN0 = cast(N0); + MVT::ValueType EVT = LN0->getLoadVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - EVT); + SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); AddToWorkList(N); CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); return SDOperand(N, 0); // Return N so it doesn't get rechecked! @@ -1093,14 +1092,15 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { } // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) { - MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); + LoadSDNode *LN0 = cast(N0); + MVT::ValueType EVT = LN0->getLoadVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - EVT); + SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); AddToWorkList(N); CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); return SDOperand(N, 0); // Return N so it doesn't get rechecked! @@ -1109,41 +1109,41 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { // fold (and (load x), 255) -> (zextload x, i8) // fold (and (extload x, i16), 255) -> (zextload x, i8) - if (N1C && - (N0.getOpcode() == ISD::LOAD || ISD::isEXTLoad(N0.Val) || - ISD::isZEXTLoad(N0.Val)) && - N0.hasOneUse()) { - MVT::ValueType EVT, LoadedVT; - if (N1C->getValue() == 255) - EVT = MVT::i8; - else if (N1C->getValue() == 65535) - EVT = MVT::i16; - else if (N1C->getValue() == ~0U) - EVT = MVT::i32; - else - EVT = MVT::Other; + if (N1C && N0.getOpcode() == ISD::LOAD) { + LoadSDNode *LN0 = cast(N0); + if (LN0->getExtensionType() != ISD::SEXTLOAD && + N0.hasOneUse()) { + MVT::ValueType EVT, LoadedVT; + if (N1C->getValue() == 255) + EVT = MVT::i8; + else if (N1C->getValue() == 65535) + EVT = MVT::i16; + else if (N1C->getValue() == ~0U) + EVT = MVT::i32; + else + EVT = MVT::Other; - LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : - cast(N0.getOperand(3))->getVT(); - if (EVT != MVT::Other && LoadedVT > EVT && - (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { - MVT::ValueType PtrType = N0.getOperand(1).getValueType(); - // For big endian targets, we need to add an offset to the pointer to load - // the correct bytes. For little endian systems, we merely need to read - // fewer bytes from the same pointer. - unsigned PtrOff = - (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; - SDOperand NewPtr = N0.getOperand(1); - if (!TLI.isLittleEndian()) - NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, - DAG.getConstant(PtrOff, PtrType)); - AddToWorkList(NewPtr.Val); - SDOperand Load = - DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, - N0.getOperand(2), EVT); - AddToWorkList(N); - CombineTo(N0.Val, Load, Load.getValue(1)); - return SDOperand(N, 0); // Return N so it doesn't get rechecked! + LoadedVT = LN0->getLoadVT(); + if (EVT != MVT::Other && LoadedVT > EVT && + (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { + MVT::ValueType PtrType = N0.getOperand(1).getValueType(); + // For big endian targets, we need to add an offset to the pointer to + // load the correct bytes. For little endian systems, we merely need to + // read fewer bytes from the same pointer. + unsigned PtrOff = + (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; + SDOperand NewPtr = LN0->getBasePtr(); + if (!TLI.isLittleEndian()) + NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, + DAG.getConstant(PtrOff, PtrType)); + AddToWorkList(NewPtr.Val); + SDOperand Load = + DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, + LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); + AddToWorkList(N); + CombineTo(N0.Val, Load, Load.getValue(1)); + return SDOperand(N, 0); // Return N so it doesn't get rechecked! + } } } @@ -1857,10 +1857,12 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { } // fold (sext (load x)) -> (sext (truncate (sextload x))) - if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && + if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ - SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), + LoadSDNode *LN0 = cast(N0); + SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), N0.getValueType()); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), @@ -1871,9 +1873,11 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { // fold (sext (sextload x)) -> (sext (truncate (sextload x))) // fold (sext ( extload x)) -> (sext (truncate (sextload x))) if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { - MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); - SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), EVT); + LoadSDNode *LN0 = cast(N0); + MVT::ValueType EVT = LN0->getLoadVT(); + SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); @@ -1922,10 +1926,12 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { } // fold (zext (load x)) -> (zext (truncate (zextload x))) - if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && + if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), + LoadSDNode *LN0 = cast(N0); + SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), N0.getValueType()); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), @@ -1936,9 +1942,11 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { // fold (zext (zextload x)) -> (zext (truncate (zextload x))) // fold (zext ( extload x)) -> (zext (truncate (zextload x))) if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { - MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); - SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), EVT); + LoadSDNode *LN0 = cast(N0); + MVT::ValueType EVT = LN0->getLoadVT(); + SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); @@ -1987,10 +1995,12 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { } // fold (aext (load x)) -> (aext (truncate (extload x))) - if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && + if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), + LoadSDNode *LN0 = cast(N0); + SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), N0.getValueType()); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), @@ -2001,12 +2011,14 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { // fold (aext (zextload x)) -> (aext (truncate (zextload x))) // fold (aext (sextload x)) -> (aext (truncate (sextload x))) // fold (aext ( extload x)) -> (aext (truncate (extload x))) - if (N0.getOpcode() == ISD::LOADX && N0.hasOneUse()) { - MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); - unsigned LType = N0.getConstantOperandVal(4); - SDOperand ExtLoad = DAG.getExtLoad((ISD::LoadExtType)LType, VT, - N0.getOperand(0), N0.getOperand(1), - N0.getOperand(2), EVT); + if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) && + N0.hasOneUse()) { + LoadSDNode *LN0 = cast(N0); + MVT::ValueType EVT = LN0->getLoadVT(); + SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, + LN0->getChain(), LN0->getBasePtr(), + LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); @@ -2057,22 +2069,24 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { // fold (sext_inreg (extload x)) -> (sextload x) if (ISD::isEXTLoad(N0.Val) && - EVT == cast(N0.getOperand(3))->getVT() && + EVT == cast(N0)->getLoadVT() && (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - EVT); + LoadSDNode *LN0 = cast(N0); + SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); return SDOperand(N, 0); // Return N so it doesn't get rechecked! } // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() && - EVT == cast(N0.getOperand(3))->getVT() && + EVT == cast(N0)->getLoadVT() && (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - EVT); + LoadSDNode *LN0 = cast(N0); + SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); return SDOperand(N, 0); // Return N so it doesn't get rechecked! @@ -2108,20 +2122,22 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { return N0.getOperand(0); } // fold (truncate (load x)) -> (smaller load x) - if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { + if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && "Cannot truncate to larger type!"); + LoadSDNode *LN0 = cast(N0); MVT::ValueType PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to load // the correct bytes. For little endian systems, we merely need to read // fewer bytes from the same pointer. uint64_t PtrOff = (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; - SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : - DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), + SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() : + DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), DAG.getConstant(PtrOff, PtrType)); AddToWorkList(NewPtr.Val); - SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); + SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr, + LN0->getSrcValue(), LN0->getSrcValueOffset()); AddToWorkList(N); CombineTo(N0.Val, Load, Load.getValue(1)); return SDOperand(N, 0); // Return N so it doesn't get rechecked! @@ -2145,9 +2161,10 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { // fold (conv (load x)) -> (load (conv*)x) // FIXME: These xforms need to know that the resultant load doesn't need a // higher alignment than the original! - if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { - SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), - N0.getOperand(2)); + if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { + LoadSDNode *LN0 = cast(N0); + SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), + LN0->getSrcValue(), LN0->getSrcValueOffset()); AddToWorkList(N); CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), Load.getValue(1)); @@ -2517,10 +2534,12 @@ SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { return DAG.getNode(ISD::FP_EXTEND, VT, N0); // fold (fpext (load x)) -> (fpext (fpround (extload x))) - if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && + if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { - SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), + LoadSDNode *LN0 = cast(N0); + SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), + LN0->getBasePtr(), LN0->getSrcValue(), + LN0->getSrcValueOffset(), N0.getValueType()); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), @@ -2616,15 +2635,18 @@ SDOperand DAGCombiner::visitBR_CC(SDNode *N) { } SDOperand DAGCombiner::visitLOAD(SDNode *N) { - SDOperand Chain = N->getOperand(0); - SDOperand Ptr = N->getOperand(1); - SDOperand SrcValue = N->getOperand(2); + LoadSDNode *LD = cast(N); + SDOperand Chain = LD->getChain(); + SDOperand Ptr = LD->getBasePtr(); // If there are no uses of the loaded value, change uses of the chain value // into uses of the chain input (i.e. delete the dead load). if (N->hasNUsesOfValue(0, 0)) return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); + if (!ISD::isNON_EXTLoad(N)) + return SDOperand(); + // If this load is directly stored, replace the load value with the stored // value. // TODO: Handle store large -> read small portion. @@ -2641,7 +2663,7 @@ SDOperand DAGCombiner::visitLOAD(SDNode *N) { if (Chain != BetterChain) { // Replace the chain to void dependency. SDOperand ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, - SrcValue); + LD->getSrcValue(), LD->getSrcValueOffset()); // Create token factor to keep old chain connected. SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, @@ -2655,21 +2677,6 @@ SDOperand DAGCombiner::visitLOAD(SDNode *N) { return SDOperand(); } -/// visitLOADX - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. -SDOperand DAGCombiner::visitLOADX(SDNode *N) { - SDOperand Chain = N->getOperand(0); - SDOperand Ptr = N->getOperand(1); - SDOperand SrcValue = N->getOperand(2); - SDOperand EVT = N->getOperand(3); - - // If there are no uses of the loaded value, change uses of the chain value - // into uses of the chain input (i.e. delete the dead load). - if (N->hasNUsesOfValue(0, 0)) - return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); - - return SDOperand(); -} - SDOperand DAGCombiner::visitSTORE(SDNode *N) { SDOperand Chain = N->getOperand(0); SDOperand Value = N->getOperand(1); @@ -3268,47 +3275,49 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, // of two loads with a load through a select of the address to load from. // This triggers in things like "select bool X, 10.0, 123.0" after the FP // constants have been dropped into the constant pool. - if ((LHS.getOpcode() == ISD::LOAD || - LHS.getOpcode() == ISD::LOADX ) && + if (LHS.getOpcode() == ISD::LOAD && // Token chains must be identical. - LHS.getOperand(0) == RHS.getOperand(0) && - // If this is an EXTLOAD, the VT's must match. - (LHS.getOpcode() == ISD::LOAD || - LHS.getOperand(3) == RHS.getOperand(3))) { - // FIXME: this conflates two src values, discarding one. This is not - // the right thing to do, but nothing uses srcvalues now. When they do, - // turn SrcValue into a list of locations. - SDOperand Addr; - if (TheSelect->getOpcode() == ISD::SELECT) - Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), - TheSelect->getOperand(0), LHS.getOperand(1), - RHS.getOperand(1)); - else - Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), - TheSelect->getOperand(0), - TheSelect->getOperand(1), - LHS.getOperand(1), RHS.getOperand(1), - TheSelect->getOperand(4)); + LHS.getOperand(0) == RHS.getOperand(0)) { + LoadSDNode *LLD = cast(LHS); + LoadSDNode *RLD = cast(RHS); + + // If this is an EXTLOAD, the VT's must match. + if (LLD->getLoadVT() == RLD->getLoadVT()) { + // FIXME: this conflates two src values, discarding one. This is not + // the right thing to do, but nothing uses srcvalues now. When they do, + // turn SrcValue into a list of locations. + SDOperand Addr; + if (TheSelect->getOpcode() == ISD::SELECT) + Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), + TheSelect->getOperand(0), LLD->getBasePtr(), + RLD->getBasePtr()); + else + Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), + TheSelect->getOperand(0), + TheSelect->getOperand(1), + LLD->getBasePtr(), RLD->getBasePtr(), + TheSelect->getOperand(4)); - SDOperand Load; - if (LHS.getOpcode() == ISD::LOAD) - Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), - Addr, LHS.getOperand(2)); - else { - unsigned LType = LHS.getConstantOperandVal(4); - Load = DAG.getExtLoad((ISD::LoadExtType)LType, - TheSelect->getValueType(0), - LHS.getOperand(0), Addr, LHS.getOperand(2), - cast(LHS.getOperand(3))->getVT()); - } - // Users of the select now use the result of the load. - CombineTo(TheSelect, Load); + SDOperand Load; + if (LLD->getExtensionType() == ISD::NON_EXTLOAD) + Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), + Addr,LLD->getSrcValue(), LLD->getSrcValueOffset()); + else { + Load = DAG.getExtLoad(LLD->getExtensionType(), + TheSelect->getValueType(0), + LLD->getChain(), Addr, LLD->getSrcValue(), + LLD->getSrcValueOffset(), + LLD->getLoadVT()); + } + // Users of the select now use the result of the load. + CombineTo(TheSelect, Load); - // Users of the old loads now use the new load's chain. We know the - // old-load value is dead now. - CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); - CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); - return true; + // Users of the old loads now use the new load's chain. We know the + // old-load value is dead now. + CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); + CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); + return true; + } } } @@ -3965,10 +3974,12 @@ static bool isAlias(SDOperand Ptr1, int64_t Size1, SDOperand SrcValue1, /// FindAliasInfo - Extracts the relevant alias information from the memory /// node. Returns true if the operand was a load. -static bool FindAliasInfo(SDNode *N, - SDOperand &Ptr, int64_t &Size, SDOperand &SrcValue) { +static bool FindAliasInfo(SDNode *N, SDOperand &Ptr, int64_t &Size, + SDOperand &SrcValue, SelectionDAG &DAG) { switch (N->getOpcode()) { case ISD::LOAD: + if (!ISD::isNON_EXTLoad(N)) + return false; Ptr = N->getOperand(1); Size = MVT::getSizeInBits(N->getValueType(0)) >> 3; SrcValue = N->getOperand(2); @@ -3997,7 +4008,7 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, SDOperand Ptr; int64_t Size; SDOperand SrcValue; - bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue); + bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, DAG); // Starting off. Chains.push_back(OriginalChain); @@ -4024,7 +4035,7 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, SDOperand OpPtr; int64_t OpSize; SDOperand OpSrcValue; - bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue); + bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue, DAG); // If chain is alias then stop here. if (!(IsLoad && IsOpLoad) && diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 71f1c2449ea..a3adb55d894 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -808,10 +808,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); if (Extend) { Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), - CPIdx, DAG.getSrcValue(NULL), MVT::f32); + CPIdx, NULL, 0, MVT::f32); } else { - Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - DAG.getSrcValue(NULL)); + Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); } } break; @@ -941,7 +940,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Store the scalar value. Ch = DAG.getStore(Ch, Tmp2, StackPtr2, DAG.getSrcValue(NULL)); // Load the updated vector. - Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL)); + Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); break; } } @@ -1335,104 +1334,106 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case ISD::LOAD: { - Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. + LoadSDNode *LD = cast(Node); + Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. + Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. - MVT::ValueType VT = Node->getValueType(0); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); - Tmp3 = Result.getValue(0); - Tmp4 = Result.getValue(1); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) { + MVT::ValueType VT = Node->getValueType(0); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); + Tmp3 = Result.getValue(0); + Tmp4 = Result.getValue(1); - switch (TLI.getOperationAction(Node->getOpcode(), VT)) { - default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Legal: break; - case TargetLowering::Custom: - Tmp1 = TLI.LowerOperation(Tmp3, DAG); - if (Tmp1.Val) { - Tmp3 = LegalizeOp(Tmp1); + switch (TLI.getOperationAction(Node->getOpcode(), VT)) { + default: assert(0 && "This action is not supported yet!"); + case TargetLowering::Legal: break; + case TargetLowering::Custom: + Tmp1 = TLI.LowerOperation(Tmp3, DAG); + if (Tmp1.Val) { + Tmp3 = LegalizeOp(Tmp1); + Tmp4 = LegalizeOp(Tmp1.getValue(1)); + } + break; + case TargetLowering::Promote: { + // Only promote a load of vector type to another. + assert(MVT::isVector(VT) && "Cannot promote this load!"); + // Change base type to a different vector type. + MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); + + Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), + LD->getSrcValueOffset()); + Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); Tmp4 = LegalizeOp(Tmp1.getValue(1)); + break; } - break; - case TargetLowering::Promote: { - // Only promote a load of vector type to another. - assert(MVT::isVector(VT) && "Cannot promote this load!"); - // Change base type to a different vector type. - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); - - Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2)); - Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); - Tmp4 = LegalizeOp(Tmp1.getValue(1)); - break; - } - } - // Since loads produce two values, make sure to remember that we - // legalized both of them. - AddLegalizedOperand(SDOperand(Node, 0), Tmp3); - AddLegalizedOperand(SDOperand(Node, 1), Tmp4); - return Op.ResNo ? Tmp4 : Tmp3; - } - case ISD::LOADX: { - Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. - - MVT::ValueType SrcVT = cast(Node->getOperand(3))->getVT(); - unsigned LType = cast(Node->getOperand(4))->getValue(); - switch (TLI.getLoadXAction(LType, SrcVT)) { - default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Promote: - assert(SrcVT == MVT::i1 && "Can only promote LOADX from i1 -> i8!"); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), - DAG.getValueType(MVT::i8), - Node->getOperand(4)); + } + // Since loads produce two values, make sure to remember that we + // legalized both of them. + AddLegalizedOperand(SDOperand(Node, 0), Tmp3); + AddLegalizedOperand(SDOperand(Node, 1), Tmp4); + return Op.ResNo ? Tmp4 : Tmp3; + } else { + MVT::ValueType SrcVT = LD->getLoadVT(); + switch (TLI.getLoadXAction(ExtType, SrcVT)) { + default: assert(0 && "This action is not supported yet!"); + case TargetLowering::Promote: + assert(SrcVT == MVT::i1 && + "Can only promote extending LOAD from i1 -> i8!"); + Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, + LD->getSrcValue(), LD->getSrcValueOffset(), + MVT::i8); Tmp1 = Result.getValue(0); Tmp2 = Result.getValue(1); break; - case TargetLowering::Custom: - isCustom = true; - // FALLTHROUGH - case TargetLowering::Legal: - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), - Node->getOperand(3), Node->getOperand(4)); - Tmp1 = Result.getValue(0); - Tmp2 = Result.getValue(1); + case TargetLowering::Custom: + isCustom = true; + // FALLTHROUGH + case TargetLowering::Legal: + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); + Tmp1 = Result.getValue(0); + Tmp2 = Result.getValue(1); - if (isCustom) { - Tmp3 = TLI.LowerOperation(Result, DAG); - if (Tmp3.Val) { - Tmp1 = LegalizeOp(Tmp3); - Tmp2 = LegalizeOp(Tmp3.getValue(1)); + if (isCustom) { + Tmp3 = TLI.LowerOperation(Result, DAG); + if (Tmp3.Val) { + Tmp1 = LegalizeOp(Tmp3); + Tmp2 = LegalizeOp(Tmp3.getValue(1)); + } } - } - break; - case TargetLowering::Expand: - // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND - if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { - SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); - Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); - Tmp1 = LegalizeOp(Result); // Relegalize new nodes. - Tmp2 = LegalizeOp(Load.getValue(1)); + break; + case TargetLowering::Expand: + // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND + if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { + SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), + LD->getSrcValueOffset()); + Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); + Tmp1 = LegalizeOp(Result); // Relegalize new nodes. + Tmp2 = LegalizeOp(Load.getValue(1)); + break; + } + assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!"); + // Turn the unsupported load into an EXTLOAD followed by an explicit + // zero/sign extend inreg. + Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), + Tmp1, Tmp2, LD->getSrcValue(), + LD->getSrcValueOffset(), SrcVT); + SDOperand ValRes; + if (ExtType == ISD::SEXTLOAD) + ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + Result, DAG.getValueType(SrcVT)); + else + ValRes = DAG.getZeroExtendInReg(Result, SrcVT); + Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. + Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. break; } - assert(LType != ISD::EXTLOAD && "EXTLOAD should always be supported!"); - // Turn the unsupported load into an EXTLOAD followed by an explicit - // zero/sign extend inreg. - Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), - Tmp1, Tmp2, Node->getOperand(2), SrcVT); - SDOperand ValRes; - if (LType == ISD::SEXTLOAD) - ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), - Result, DAG.getValueType(SrcVT)); - else - ValRes = DAG.getZeroExtendInReg(Result, SrcVT); - Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. - Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. - break; + // Since loads produce two values, make sure to remember that we legalized + // both of them. + AddLegalizedOperand(SDOperand(Node, 0), Tmp1); + AddLegalizedOperand(SDOperand(Node, 1), Tmp2); + return Op.ResNo ? Tmp2 : Tmp1; } - // Since loads produce two values, make sure to remember that we legalized - // both of them. - AddLegalizedOperand(SDOperand(Node, 0), Tmp1); - AddLegalizedOperand(SDOperand(Node, 1), Tmp2); - return Op.ResNo ? Tmp2 : Tmp1; } case ISD::EXTRACT_ELEMENT: { MVT::ValueType OpTy = Node->getOperand(0).getValueType(); @@ -2387,8 +2388,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case TargetLowering::Expand: { + SrcValueSDNode *SV = cast(Node->getOperand(2)); SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, - Node->getOperand(2)); + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, @@ -2396,7 +2398,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2)); // Load the actual argument out of the pointer VAList - Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); + Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); Tmp1 = LegalizeOp(Result.getValue(1)); Result = LegalizeOp(Result); break; @@ -2430,7 +2432,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: // This defaults to loading a pointer from the input and storing it to the // output, returning the chain. - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); + SrcValueSDNode *SVD = cast(Node->getOperand(3)); + SrcValueSDNode *SVS = cast(Node->getOperand(4)); + Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), + SVD->getOffset()); Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, Node->getOperand(4)); break; } @@ -2874,8 +2879,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Node->getOperand(0), StackSlot, DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), - Result, StackSlot, DAG.getSrcValue(NULL), - ExtraVT); + Result, StackSlot, NULL, 0, ExtraVT); } else { assert(0 && "Unknown op"); } @@ -3212,8 +3216,9 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); Result = TLI.CustomPromoteOperation(Tmp3, DAG); } else { + SrcValueSDNode *SV = cast(Node->getOperand(2)); SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, - Node->getOperand(2)); + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, @@ -3221,28 +3226,20 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, Node->getOperand(2)); // Load the actual argument out of the pointer VAList - Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, - DAG.getSrcValue(0), VT); + Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); } // Remember that we legalized the chain. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); break; - case ISD::LOAD: - Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), - Node->getOperand(1), Node->getOperand(2), VT); - // Remember that we legalized the chain. - AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); - break; - case ISD::LOADX: - Result = - DAG.getExtLoad((ISD::LoadExtType)Node->getConstantOperandVal(4), - NVT, Node->getOperand(0), Node->getOperand(1), - Node->getOperand(2), - cast(Node->getOperand(3))->getVT()); + case ISD::LOAD: { + LoadSDNode *LD = cast(Node); + Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, LD->getChain(), LD->getBasePtr(), + LD->getSrcValue(), LD->getSrcValueOffset(), VT); // Remember that we legalized the chain. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); break; + } case ISD::SELECT: Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 @@ -3370,7 +3367,7 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { DAG.getConstant(EltSize, Idx.getValueType())); StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); - return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL)); + return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); } @@ -3508,7 +3505,7 @@ SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, DAG.getSrcValue(NULL)); // Result is a load from the stack slot. - return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); + return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); } SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { @@ -3517,7 +3514,7 @@ SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, DAG.getSrcValue(NULL)); - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL)); + return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); } @@ -3581,8 +3578,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { } Constant *CP = ConstantPacked::get(CV); SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - DAG.getSrcValue(NULL)); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); } if (SplatValue.Val) { // Splat of one value? @@ -3677,7 +3673,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { StoreChain = DAG.getEntryNode(); // Result is a load from the stack slot. - return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0)); + return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); } /// CreateStackTemporary - Create a stack temporary, suitable for holding the @@ -3933,12 +3929,11 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestTy == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, - DAG.getSrcValue(NULL)); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); else { assert(DestTy == MVT::f64 && "Unexpected conversion"); FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), - CPIdx, DAG.getSrcValue(NULL), MVT::f32); + CPIdx, NULL, 0, MVT::f32); } return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); } @@ -4017,8 +4012,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, // store the hi of the constructed double - biased exponent SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, DAG.getSrcValue(NULL)); // load the constructed double - SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, - DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); // FP constant to bias correct the final result SDOperand Bias = DAG.getConstantFP(isSigned ? BitsToDouble(0x4330000080000000ULL) @@ -4066,13 +4060,12 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestVT == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, - DAG.getSrcValue(NULL)); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); else { assert(DestVT == MVT::f64 && "Unexpected conversion"); FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, - DAG.getSrcValue(NULL), MVT::f32)); + NULL, 0, MVT::f32)); } return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); @@ -4420,26 +4413,57 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ } case ISD::LOAD: { - SDOperand Ch = Node->getOperand(0); // Legalize the chain. - SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. - Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); - - // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; - Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, - getIntPtrConstant(IncrementSize)); - // FIXME: This creates a bogus srcvalue! - Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); - - // Build a factor node to remember that this load is independent of the - // other one. - SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), - Hi.getValue(1)); - - // Remember that we legalized the chain. - AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); - if (!TLI.isLittleEndian()) - std::swap(Lo, Hi); + LoadSDNode *LD = cast(Node); + SDOperand Ch = LD->getChain(); // Legalize the chain. + SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. + ISD::LoadExtType ExtType = LD->getExtensionType(); + + if (ExtType == ISD::NON_EXTLOAD) { + Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); + + // Increment the pointer to the other half. + unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; + Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, + getIntPtrConstant(IncrementSize)); + // FIXME: This creates a bogus srcvalue! + Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); + + // Build a factor node to remember that this load is independent of the + // other one. + SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), + Hi.getValue(1)); + + // Remember that we legalized the chain. + AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); + if (!TLI.isLittleEndian()) + std::swap(Lo, Hi); + } else { + MVT::ValueType EVT = LD->getLoadVT(); + + if (EVT == NVT) + Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), + LD->getSrcValueOffset()); + else + Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), + LD->getSrcValueOffset(), EVT); + + // Remember that we legalized the chain. + AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); + + if (ExtType == ISD::SEXTLOAD) { + // The high part is obtained by SRA'ing all but one of the bits of the + // lo part. + unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + Hi = DAG.getNode(ISD::SRA, NVT, Lo, + DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); + } else if (ExtType == ISD::ZEXTLOAD) { + // The high part is just a zero. + Hi = DAG.getConstant(0, NVT); + } else /* if (ExtType == ISD::EXTLOAD) */ { + // The high part is undefined. + Hi = DAG.getNode(ISD::UNDEF, NVT); + } + } break; } case ISD::AND: @@ -4470,35 +4494,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ Node->getOperand(1), TH, FH, Node->getOperand(4)); break; } - case ISD::LOADX: { - SDOperand Chain = Node->getOperand(0); - SDOperand Ptr = Node->getOperand(1); - MVT::ValueType EVT = cast(Node->getOperand(3))->getVT(); - ISD::LoadExtType LType = (ISD::LoadExtType)Node->getConstantOperandVal(4); - - if (EVT == NVT) - Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); - else - Lo = DAG.getExtLoad(LType, NVT, Chain, Ptr, Node->getOperand(2), EVT); - - // Remember that we legalized the chain. - AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); - - if (LType == ISD::SEXTLOAD) { - // The high part is obtained by SRA'ing all but one of the bits of the lo - // part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); - Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, - TLI.getShiftAmountTy())); - } else if (LType == ISD::ZEXTLOAD) { - // The high part is just a zero. - Hi = DAG.getConstant(0, NVT); - } else /* if (LType == ISD::EXTLOAD) */ { - // The high part is undefined. - Hi = DAG.getNode(ISD::UNDEF, NVT); - } - break; - } case ISD::ANY_EXTEND: // The low part is any extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); @@ -4995,7 +4990,8 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. - Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2)); + SrcValueSDNode *SV = cast(Node->getOperand(2)); + Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset()); // Remember that we legalized the chain. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index e673175172d..2b7a9db73ab 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1460,14 +1460,66 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, SDOperand SelectionDAG::getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, - SDOperand SV) { + const Value *SV, int SVOffset, + bool isVolatile) { + // FIXME: Alignment == 1 for now. + unsigned Alignment = 1; SDVTList VTs = getVTList(VT, MVT::Other); - - SelectionDAGCSEMap::NodeID ID(ISD::LOAD, VTs, Chain, Ptr, SV); + SDOperand Undef = getNode(ISD::UNDEF, VT); + SelectionDAGCSEMap::NodeID ID(ISD::LOAD, VTs, Chain, Ptr, Undef); + ID.AddInteger(ISD::UNINDEXED); + ID.AddInteger(ISD::NON_EXTLOAD); + ID.AddInteger(VT); + ID.AddPointer(SV); + ID.AddInteger(SVOffset); + ID.AddInteger(Alignment); + ID.AddInteger(isVolatile); + void *IP = 0; + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) + return SDOperand(E, 0); + SDNode *N = new LoadSDNode(Chain, Ptr, Undef, ISD::NON_EXTLOAD, VT, + SV, SVOffset, Alignment, isVolatile); + N->setValueTypes(VTs); + CSEMap.InsertNode(N, IP); + AllNodes.push_back(N); + return SDOperand(N, 0); +} + +SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, + SDOperand Chain, SDOperand Ptr, const Value *SV, + int SVOffset, MVT::ValueType EVT, + bool isVolatile) { + // If they are asking for an extending load from/to the same thing, return a + // normal load. + if (VT == EVT) + ExtType = ISD::NON_EXTLOAD; + + if (MVT::isVector(VT)) + assert(EVT == MVT::getVectorBaseType(VT) && "Invalid vector extload!"); + else + assert(EVT < VT && "Should only be an extending load, not truncating!"); + assert((ExtType == ISD::EXTLOAD || MVT::isInteger(VT)) && + "Cannot sign/zero extend a FP/Vector load!"); + assert(MVT::isInteger(VT) == MVT::isInteger(EVT) && + "Cannot convert from FP to Int or Int -> FP!"); + + // FIXME: Alignment == 1 for now. + unsigned Alignment = 1; + SDVTList VTs = getVTList(VT, MVT::Other); + SDOperand Undef = getNode(ISD::UNDEF, VT); + SelectionDAGCSEMap::NodeID ID(ISD::LOAD, VTs, Chain, Ptr, Undef); + ID.AddInteger(ISD::UNINDEXED); + ID.AddInteger(ExtType); + ID.AddInteger(EVT); + ID.AddPointer(SV); + ID.AddInteger(SVOffset); + ID.AddInteger(Alignment); + ID.AddInteger(isVolatile); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); - SDNode *N = new SDNode(ISD::LOAD, Chain, Ptr, SV); + SDNode *N = new LoadSDNode(Chain, Ptr, Undef, ExtType, EVT, SV, SVOffset, + Alignment, isVolatile); N->setValueTypes(VTs); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); @@ -1482,14 +1534,6 @@ SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT, return getNode(ISD::VLOAD, getVTList(MVT::Vector, MVT::Other), Ops, 5); } -SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType LType, MVT::ValueType VT, - SDOperand Chain, SDOperand Ptr, SDOperand SV, - MVT::ValueType EVT) { - SDOperand Ops[] = { Chain, Ptr, SV, getValueType(EVT), - getConstant(LType, MVT::i32) }; - return getNode(ISD::LOADX, getVTList(VT, MVT::Other), Ops, 5); -} - SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Value, SDOperand Ptr, SDOperand SV) { SDVTList VTs = getVTList(MVT::Other); @@ -1602,28 +1646,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, return getNode(Opcode, VTList.VTs[0], Ops, NumOps); switch (Opcode) { - case ISD::LOADX: { - MVT::ValueType EVT = cast(Ops[3])->getVT(); - unsigned LType = cast(Ops[4])->getValue(); - assert(NumOps == 5 && VTList.NumVTs == 2 && "Bad *EXTLOAD!"); - // If they are asking for an extending load from/to the same thing, return a - // normal load. - if (VTList.VTs[0] == EVT) - return getLoad(VTList.VTs[0], Ops[0], Ops[1], Ops[2]); - if (MVT::isVector(VTList.VTs[0])) { - assert(EVT == MVT::getVectorBaseType(VTList.VTs[0]) && - "Invalid vector extload!"); - } else { - assert(EVT < VTList.VTs[0] && - "Should only be an extending load, not truncating!"); - } - assert((LType == ISD::EXTLOAD || MVT::isInteger(VTList.VTs[0])) && - "Cannot sign/zero extend a FP/Vector load!"); - assert(MVT::isInteger(VTList.VTs[0]) == MVT::isInteger(EVT) && - "Cannot convert from FP to Int or Int -> FP!"); - break; - } - // FIXME: figure out how to safely handle things like // int foo(int x) { return 1 << (x & 255); } // int bar() { return foo(256); } @@ -2545,7 +2567,6 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const { case ISD::LOAD: return "load"; case ISD::STORE: return "store"; case ISD::VLOAD: return "vload"; - case ISD::LOADX: return "loadx"; case ISD::TRUNCSTORE: return "truncstore"; case ISD::VAARG: return "vaarg"; case ISD::VACOPY: return "vacopy"; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 6d0f782220b..e17105c0f03 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -460,7 +460,7 @@ public: void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; } SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr, - SDOperand SrcValue, SDOperand Root, + const Value *SV, SDOperand Root, bool isVolatile); SDOperand getIntPtrConstant(uint64_t Val) { @@ -859,7 +859,7 @@ void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy); SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB); SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD, - DAG.getSrcValue(0)); + NULL, 0); if (isPIC) { // For Pic, the sequence is: // BRIND(load(Jumptable + index) + RelocBase) @@ -1360,19 +1360,20 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { Root = DAG.getRoot(); } - setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)), + setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0), Root, I.isVolatile())); } SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr, - SDOperand SrcValue, SDOperand Root, + const Value *SV, SDOperand Root, bool isVolatile) { SDOperand L; if (const PackedType *PTy = dyn_cast(Ty)) { MVT::ValueType PVT = TLI.getValueType(PTy->getElementType()); - L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue); + L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, + DAG.getSrcValue(SV)); } else { - L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue); + L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile); } if (isVolatile) @@ -2909,7 +2910,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) { } else { Value = DAG.getLoad(VT, getRoot(), getMemBasePlusOffset(Op2, SrcOff, DAG, TLI), - DAG.getSrcValue(I.getOperand(2), SrcOff)); + I.getOperand(2), SrcOff); Chain = Value.getValue(1); Store = DAG.getStore(Chain, Value, diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 1c00c9136c3..73cefc4e385 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -552,9 +552,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, KnownOne = 0; break; } - case ISD::LOADX: { + case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { - MVT::ValueType VT = cast(Op.getOperand(3))->getVT(); + LoadSDNode *LD = cast(Op); + MVT::ValueType VT = LD->getLoadVT(); KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; } break; @@ -892,9 +893,10 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, KnownOne = 0; return; } - case ISD::LOADX: { + case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { - MVT::ValueType VT = cast(Op.getOperand(3))->getVT(); + LoadSDNode *LD = cast(Op); + MVT::ValueType VT = LD->getLoadVT(); KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; } return; @@ -1197,15 +1199,16 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ } // Handle LOADX separately here. EXTLOAD case will fallthrough. - if (Op.getOpcode() == ISD::LOADX) { - unsigned LType = Op.getConstantOperandVal(4); - switch (LType) { + if (Op.getOpcode() == ISD::LOAD) { + LoadSDNode *LD = cast(Op); + unsigned ExtType = LD->getExtensionType(); + switch (ExtType) { default: break; case ISD::SEXTLOAD: // '17' bits known - Tmp = MVT::getSizeInBits(cast(Op.getOperand(3))->getVT()); + Tmp = MVT::getSizeInBits(LD->getLoadVT()); return VTBits-Tmp+1; case ISD::ZEXTLOAD: // '16' bits known - Tmp = MVT::getSizeInBits(cast(Op.getOperand(3))->getVT()); + Tmp = MVT::getSizeInBits(LD->getLoadVT()); return VTBits-Tmp; } } diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index ccbe5941893..b3d1cfbe7d1 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -420,8 +420,7 @@ static SDOperand LowerGlobalAddress(SDOperand Op, GlobalValue *GV = cast(Op)->getGlobal(); int alignment = 2; SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment); - return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, - DAG.getSrcValue(NULL)); + return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, NULL, 0); } static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, @@ -479,7 +478,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, unsigned Size = MVT::getSizeInBits(VT)/8; int FI = MFI->CreateFixedObject(Size, Offset); SDOperand FIN = DAG.getFrameIndex(FI, VT); - Value = DAG.getLoad(VT, Root, FIN, DAG.getSrcValue(NULL)); + Value = DAG.getLoad(VT, Root, FIN, NULL, 0); } else { Value = DAG.getNode(ISD::UNDEF, VT); } diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 068e6b2725f..dfa1e2f57c3 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -254,7 +254,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, // Create the SelectionDAG nodes corresponding to a load //from this parameter SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL)); + ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); } ArgValues.push_back(ArgVal); } @@ -430,7 +430,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64); SDOperand ST = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), FI, DAG.getSrcValue(0)); - LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0)); + LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0); } SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, isDouble?MVT::f64:MVT::f32, LD); @@ -453,7 +453,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64); SDOperand ST = DAG.getStore(DAG.getEntryNode(), src, FI, DAG.getSrcValue(0)); - return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0)); + return DAG.getLoad(MVT::i64, ST, FI, NULL, 0); } } case ISD::ConstantPool: { @@ -523,13 +523,14 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::VAARG: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - SDOperand VAListS = Op.getOperand(2); + SrcValueSDNode *VAListS = cast(Op.getOperand(2)); - SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS); + SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(), + VAListS->getOffset()); SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), - Tmp, DAG.getSrcValue(0), MVT::i32); + Tmp, NULL, 0, MVT::i32); SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); if (MVT::isFloatingPoint(Op.getValueType())) { @@ -551,10 +552,9 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand Result; if (Op.getValueType() == MVT::i32) Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr, - DAG.getSrcValue(0), MVT::i32); + NULL, 0, MVT::i32); else - Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, - DAG.getSrcValue(0)); + Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0); return Result; } case ISD::VACOPY: { @@ -562,14 +562,14 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand DestP = Op.getOperand(1); SDOperand SrcP = Op.getOperand(2); SDOperand DestS = Op.getOperand(3); - SDOperand SrcS = Op.getOperand(4); + SrcValueSDNode *SrcS = cast(Op.getOperand(4)); - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS); + SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, + SrcS->getValue(), SrcS->getOffset()); SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS); SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); - Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, - DAG.getSrcValue(0), MVT::i32); + Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, DAG.getConstant(8, MVT::i64)); return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1), diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index ceac0562d1b..60689569637 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -484,17 +484,17 @@ def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)", def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow", [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)", - [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))], s_ild>; + [(set GPRC:$RA, (sextloadi32 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow", - [(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32))], s_ild>; + [(set GPRC:$RA, (sextloadi32 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)", - [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))], s_ild>; + [(set GPRC:$RA, (zextloadi8 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow", - [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8))], s_ild>; + [(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)", - [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))], s_ild>; + [(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow", - [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16))], s_ild>; + [(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)", [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)], s_ist>; def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow", @@ -548,11 +548,11 @@ def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow", //constpool rels def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))), (LDQr tconstpool:$DISP, GPRC:$RB)>; -def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)), +def : Pat<(i64 (sextloadi32 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))), (LDLr tconstpool:$DISP, GPRC:$RB)>; -def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)), +def : Pat<(i64 (zextloadi8 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))), (LDBUr tconstpool:$DISP, GPRC:$RB)>; -def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)), +def : Pat<(i64 (zextloadi16 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))), (LDWUr tconstpool:$DISP, GPRC:$RB)>; def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)), (LDAr tconstpool:$DISP, GPRC:$RB)>; @@ -571,11 +571,11 @@ def : Pat<(i64 (Alpha_gprello tjumptable:$DISP, GPRC:$RB)), //misc ext patterns -def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)), +def : Pat<(i64 (extloadi8 (add GPRC:$RB, immSExt16:$DISP))), (LDBU immSExt16:$DISP, GPRC:$RB)>; -def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i16)), +def : Pat<(i64 (extloadi16 (add GPRC:$RB, immSExt16:$DISP))), (LDWU immSExt16:$DISP, GPRC:$RB)>; -def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i32)), +def : Pat<(i64 (extloadi32 (add GPRC:$RB, immSExt16:$DISP))), (LDL immSExt16:$DISP, GPRC:$RB)>; //0 disp patterns @@ -585,17 +585,17 @@ def : Pat<(f64 (load GPRC:$addr)), (LDT 0, GPRC:$addr)>; def : Pat<(f32 (load GPRC:$addr)), (LDS 0, GPRC:$addr)>; -def : Pat<(i64 (sextload GPRC:$addr, i32)), +def : Pat<(i64 (sextloadi32 GPRC:$addr)), (LDL 0, GPRC:$addr)>; -def : Pat<(i64 (zextload GPRC:$addr, i16)), +def : Pat<(i64 (zextloadi16 GPRC:$addr)), (LDWU 0, GPRC:$addr)>; -def : Pat<(i64 (zextload GPRC:$addr, i8)), +def : Pat<(i64 (zextloadi8 GPRC:$addr)), (LDBU 0, GPRC:$addr)>; -def : Pat<(i64 (extload GPRC:$addr, i8)), +def : Pat<(i64 (extloadi8 GPRC:$addr)), (LDBU 0, GPRC:$addr)>; -def : Pat<(i64 (extload GPRC:$addr, i16)), +def : Pat<(i64 (extloadi16 GPRC:$addr)), (LDWU 0, GPRC:$addr)>; -def : Pat<(i64 (extload GPRC:$addr, i32)), +def : Pat<(i64 (extloadi32 GPRC:$addr)), (LDL 0, GPRC:$addr)>; def : Pat<(store GPRC:$DATA, GPRC:$addr), diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 5add5d6ed5f..79252bcbaef 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -453,15 +453,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { } */ - case ISD::LOAD: - case ISD::LOADX: { // FIXME: load -1, not 1, for bools? - SDOperand Chain = N->getOperand(0); - SDOperand Address = N->getOperand(1); + case ISD::LOAD: { // FIXME: load -1, not 1, for bools? + LoadSDNode *LD = cast(N); + SDOperand Chain = LD->getChain(); + SDOperand Address = LD->getBasePtr(); AddToISelQueue(Chain); AddToISelQueue(Address); - MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ? - N->getValueType(0) : cast(N->getOperand(3))->getVT(); + MVT::ValueType TypeBeingLoaded = LD->getLoadVT(); unsigned Opc; switch (TypeBeingLoaded) { default: diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 47421a516f5..450a47bfec8 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -133,7 +133,7 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const { static bool isFloatingPointZero(SDOperand Op) { if (ConstantFPSDNode *CFP = dyn_cast(Op)) return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); - else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { + else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { // Maybe this has already been legalized into the constant pool? if (ConstantPoolSDNode *CP = dyn_cast(Op.getOperand(1))) if (ConstantFP *CFP = dyn_cast(CP->getConstVal())) @@ -226,7 +226,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { //from this parameter SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); argt = newroot = DAG.getLoad(getValueType(I->getType()), - DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); + DAG.getEntryNode(), FIN, NULL, 0); } ++count; DAG.setRoot(newroot.getValue(1)); @@ -583,8 +583,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { } case ISD::VAARG: { MVT::ValueType VT = getPointerTy(); + SrcValueSDNode *SV = cast(Op.getOperand(2)); SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), - Op.getOperand(2)); + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, @@ -593,7 +594,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, Op.getOperand(1), Op.getOperand(2)); // Load the actual argument out of the pointer VAList - return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0)); + return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9624e66be8e..900dd3cdc9f 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -311,7 +311,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { static bool isFloatingPointZero(SDOperand Op) { if (ConstantFPSDNode *CFP = dyn_cast(Op)) return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); - else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) { + else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { // Maybe this has already been legalized into the constant pool? if (ConstantPoolSDNode *CP = dyn_cast(Op.getOperand(1))) if (ConstantFP *CFP = dyn_cast(CP->getConstVal())) @@ -694,7 +694,7 @@ static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { // If the global is weak or external, we have to go through the lazy // resolution stub. - return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); + return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); } static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { @@ -873,8 +873,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, - DAG.getSrcValue(NULL)); + ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); } else { // Don't emit a dead load. ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); @@ -1051,16 +1050,14 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { // Float varargs are always shadowed in available integer registers if (GPR_idx != NumGPRs) { - SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, - DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) { SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, - DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } @@ -1401,7 +1398,7 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { DAG.getEntryNode(), Ext64, FIdx, DAG.getSrcValue(NULL)); // Load the value as a double. - SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); + SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); // FCFID it and return it. SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); @@ -2124,7 +2121,7 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { SDOperand Store = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); // Load it out. - return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); + return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); } static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { @@ -2383,18 +2380,20 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, break; case ISD::BSWAP: // Turn BSWAP (LOAD) -> lhbrx/lwbrx. - if (N->getOperand(0).getOpcode() == ISD::LOAD && + if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && N->getOperand(0).hasOneUse() && (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { SDOperand Load = N->getOperand(0); + LoadSDNode *LD = cast(Load); // Create the byte-swapping load. std::vector VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Other); + SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); SDOperand Ops[] = { - Load.getOperand(0), // Chain - Load.getOperand(1), // Ptr - Load.getOperand(2), // SrcValue + LD->getChain(), // Chain + LD->getBasePtr(), // Ptr + SV, // SrcValue DAG.getValueType(N->getValueType(0)) // VT }; SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index d822c66ead6..762a754b4e2 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -233,41 +233,41 @@ let isLoad = 1, PPC970_Unit = 2 in { // Sign extending loads. def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src), "lha $rD, $src", LdStLHA, - [(set G8RC:$rD, (sextload iaddr:$src, i16))]>, + [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src), "lwa $rD, $src", LdStLWA, - [(set G8RC:$rD, (sextload ixaddr:$src, i32))]>, isPPC64, + [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src), "lhax $rD, $src", LdStLHA, - [(set G8RC:$rD, (sextload xaddr:$src, i16))]>, + [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), "lwax $rD, $src", LdStLHA, - [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64, + [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; // Zero extending loads. def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src), "lbz $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload iaddr:$src, i8))]>; + [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src), "lhz $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload iaddr:$src, i16))]>; + [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src), "lwz $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload iaddr:$src, i32))]>, isPPC64; + [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src), "lbzx $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload xaddr:$src, i8))]>; + [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src), "lhzx $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload xaddr:$src, i16))]>; + [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src), "lwzx $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload xaddr:$src, i32))]>; + [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; // Full 8-byte loads. @@ -397,25 +397,25 @@ def : Pat<(i32 (trunc G8RC:$in)), (OR8To4 G8RC:$in, G8RC:$in)>; // Extending loads with i64 targets. -def : Pat<(zextload iaddr:$src, i1), +def : Pat<(zextloadi1 iaddr:$src), (LBZ8 iaddr:$src)>; -def : Pat<(zextload xaddr:$src, i1), +def : Pat<(zextloadi1 xaddr:$src), (LBZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i1), +def : Pat<(extloadi1 iaddr:$src), (LBZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i1), +def : Pat<(extloadi1 xaddr:$src), (LBZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i8), +def : Pat<(extloadi8 iaddr:$src), (LBZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i8), +def : Pat<(extloadi8 xaddr:$src), (LBZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i16), +def : Pat<(extloadi16 iaddr:$src), (LHZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i16), +def : Pat<(extloadi16 xaddr:$src), (LHZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i32), +def : Pat<(extloadi32 iaddr:$src), (LWZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i32), +def : Pat<(extloadi32 xaddr:$src), (LWZX8 xaddr:$src)>; // SHL/SRL diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 4c6b36b6804..f346717a3d7 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -379,14 +379,14 @@ def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), let isLoad = 1, PPC970_Unit = 2 in { def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), "lbz $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload iaddr:$src, i8))]>; + [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), "lha $rD, $src", LdStLHA, - [(set GPRC:$rD, (sextload iaddr:$src, i16))]>, + [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), "lhz $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload iaddr:$src, i16))]>; + [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), "lwz $rD, $src", LdStGeneral, [(set GPRC:$rD, (load iaddr:$src))]>; @@ -490,14 +490,14 @@ def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst), let isLoad = 1, PPC970_Unit = 2 in { def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), "lbzx $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload xaddr:$src, i8))]>; + [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), "lhax $rD, $src", LdStLHA, - [(set GPRC:$rD, (sextload xaddr:$src, i16))]>, + [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), "lhzx $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload xaddr:$src, i16))]>; + [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), "lwzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (load xaddr:$src))]>; @@ -990,25 +990,25 @@ def : Pat<(srl GPRC:$rS, GPRC:$rB), def : Pat<(shl GPRC:$rS, GPRC:$rB), (SLW GPRC:$rS, GPRC:$rB)>; -def : Pat<(zextload iaddr:$src, i1), +def : Pat<(zextloadi1 iaddr:$src), (LBZ iaddr:$src)>; -def : Pat<(zextload xaddr:$src, i1), +def : Pat<(zextloadi1 xaddr:$src), (LBZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, i1), +def : Pat<(extloadi1 iaddr:$src), (LBZ iaddr:$src)>; -def : Pat<(extload xaddr:$src, i1), +def : Pat<(extloadi1 xaddr:$src), (LBZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, i8), +def : Pat<(extloadi8 iaddr:$src), (LBZ iaddr:$src)>; -def : Pat<(extload xaddr:$src, i8), +def : Pat<(extloadi8 xaddr:$src), (LBZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, i16), +def : Pat<(extloadi16 iaddr:$src), (LHZ iaddr:$src)>; -def : Pat<(extload xaddr:$src, i16), +def : Pat<(extloadi16 xaddr:$src), (LHZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, f32), +def : Pat<(extloadf32 iaddr:$src), (FMRSD (LFS iaddr:$src))>; -def : Pat<(extload xaddr:$src, f32), +def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; include "PPCInstrAltivec.td" diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 84bad9a9d17..c92a19bf7e7 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -330,7 +330,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); SDOperand Load; if (ObjectVT == MVT::i32) { - Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); + Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } else { ISD::LoadExtType LoadOp = I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; @@ -340,7 +340,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, DAG.getConstant(Offset, MVT::i32)); Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, - DAG.getSrcValue(0), ObjectVT); + NULL, 0, ObjectVT); Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); } ArgValues.push_back(Load); @@ -363,7 +363,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); + SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); ArgValues.push_back(Load); } ArgOffset += 4; @@ -384,8 +384,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // because the double wouldn't be aligned! int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, - DAG.getSrcValue(0))); + ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); } else { SDOperand HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR @@ -395,7 +394,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); + HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } SDOperand LoVal; @@ -406,7 +405,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); + LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); } // Compose the two halves together into an i64 unit. @@ -794,8 +793,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType VT = Node->getValueType(0); SDOperand InChain = Node->getOperand(0); SDOperand VAListPtr = Node->getOperand(1); + SrcValueSDNode *SV = cast(Node->getOperand(2)); SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, - Node->getOperand(2)); + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, @@ -806,10 +806,10 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { // Load the actual argument out of the pointer VAList, unless this is an // f64 load. if (VT != MVT::f64) { - return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0)); + return DAG.getLoad(VT, InChain, VAList, NULL, 0); } else { // Otherwise, load it as i64, then do a bitconvert. - SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0)); + SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); std::vector Tys; Tys.push_back(MVT::f64); Tys.push_back(MVT::Other); diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 0137a0d6224..6fc44819348 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -278,35 +278,35 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { def LDSBrr : F3_1<3, 0b001001, (ops IntRegs:$dst, MEMrr:$addr), "ldsb [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; + [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; def LDSBri : F3_2<3, 0b001001, (ops IntRegs:$dst, MEMri:$addr), "ldsb [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; + [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; def LDSHrr : F3_1<3, 0b001010, (ops IntRegs:$dst, MEMrr:$addr), "ldsh [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; + [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; def LDSHri : F3_2<3, 0b001010, (ops IntRegs:$dst, MEMri:$addr), "ldsh [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; + [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; def LDUBrr : F3_1<3, 0b000001, (ops IntRegs:$dst, MEMrr:$addr), "ldub [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; + [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; def LDUBri : F3_2<3, 0b000001, (ops IntRegs:$dst, MEMri:$addr), "ldub [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; + [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; def LDUHrr : F3_1<3, 0b000010, (ops IntRegs:$dst, MEMrr:$addr), "lduh [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; + [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; def LDUHri : F3_2<3, 0b000010, (ops IntRegs:$dst, MEMri:$addr), "lduh [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; + [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; def LDrr : F3_1<3, 0b000000, (ops IntRegs:$dst, MEMrr:$addr), "ld [$addr], $dst", @@ -760,16 +760,16 @@ def : Pat<(call texternalsym:$dst), def : Pat<(ret), (RETL)>; // Map integer extload's to zextloads. -def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; -def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; -def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; -def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; -def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; -def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; +def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; +def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; // zextload bool -> zextload byte -def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; -def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; // truncstore bool -> truncstore byte. def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index 2a2bd17bcf3..6e9a695a93d 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -164,12 +164,6 @@ def SDTStore : SDTypeProfile<0, 2, [ // store SDTCisPtrTy<1> ]>; -def SDTLoadX : SDTypeProfile<1, 4, [ // loadX - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisVT<4, i32> -]>; -def SDTIntExtLoad : SDTypeProfile<1, 3, [ // extload, sextload, zextload - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> -]>; def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; @@ -305,12 +299,10 @@ def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>; -def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; +// Do not use ld directly. Use load, extload, sextload, zextload (see below). +def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; -// Do not use loadx directly. Use extload, sextload and zextload (see below) -// which pass in a dummy srcvalue node which tblgen will skip over. -def loadx : SDNode<"ISD::LOADX" , SDTLoadX, [SDNPHasChain]>; def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; @@ -412,13 +404,79 @@ def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; +def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + return ISD::isNON_EXTLoad(N); +}]>; + // extending load & truncstore fragments. -def extload : PatFrag<(ops node:$ptr, node:$vt), - (loadx node:$ptr, srcvalue:$dummy, node:$vt, 0)>; -def sextload : PatFrag<(ops node:$ptr, node:$vt), - (loadx node:$ptr, srcvalue:$dummy, node:$vt, 1)>; -def zextload : PatFrag<(ops node:$ptr, node:$vt), - (loadx node:$ptr, srcvalue:$dummy, node:$vt, 2)>; +def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i1; + return false; +}]>; +def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i8; + return false; +}]>; +def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i16; + return false; +}]>; +def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i32; + return false; +}]>; +def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::f32; + return false; +}]>; + +def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isSEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i1; + return false; +}]>; +def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isSEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i8; + return false; +}]>; +def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isSEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i16; + return false; +}]>; +def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isSEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i32; + return false; +}]>; + +def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isZEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i1; + return false; +}]>; +def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isZEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i8; + return false; +}]>; +def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isZEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i16; + return false; +}]>; +def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ + if (ISD::isZEXTLoad(N)) + return cast(N)->getLoadVT() == MVT::i32; + return false; +}]>; + def truncstore : PatFrag<(ops node:$val, node:$ptr, node:$vt), (truncst node:$val, node:$ptr, srcvalue:$dummy, node:$vt)>; diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 785af30e3a7..d5172566a7c 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -346,9 +346,9 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) { case ISD::ADDE: { SDOperand N10 = N1.getOperand(0); SDOperand N11 = N1.getOperand(1); - if (N10.Val->getOpcode() == ISD::LOAD) + if (ISD::isNON_EXTLoad(N10.Val)) RModW = true; - else if (N11.Val->getOpcode() == ISD::LOAD) { + else if (ISD::isNON_EXTLoad(N11.Val)) { RModW = true; std::swap(N10, N11); } @@ -370,7 +370,7 @@ void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) { case X86ISD::SHLD: case X86ISD::SHRD: { SDOperand N10 = N1.getOperand(0); - if (N10.Val->getOpcode() == ISD::LOAD) + if (ISD::isNON_EXTLoad(N10.Val)) RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() && (N10.getOperand(1) == N2) && (N10.Val->getValueType(0) == N1.getValueType()); @@ -806,7 +806,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N, SDOperand &Base, SDOperand &Scale, SDOperand &Index, SDOperand &Disp) { - if (N.getOpcode() == ISD::LOAD && + if (ISD::isNON_EXTLoad(N.Val) && N.hasOneUse() && CanBeFoldedBy(N.Val, P.Val)) return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index cd8fba9ef9d..7abfc58d00d 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -490,8 +490,7 @@ SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) // Create the frame index object for this incoming parameter... int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); ArgValues.push_back(ArgValue); ArgOffset += ArgIncrement; // Move on to the next argument... } @@ -763,8 +762,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) { Ops.push_back(DAG.getValueType(RetVT)); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - RetVal = DAG.getLoad(RetVT, Chain, StackSlot, - DAG.getSrcValue(NULL)); + RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0); Chain = RetVal.getValue(1); } @@ -963,8 +961,7 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { // parameter. int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); ArgOffset += ArgIncrement; // Move on to the next argument. } @@ -1470,11 +1467,10 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) { SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); if (ObjectVT == MVT::i64 && ObjIntRegs) { SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + NULL, 0); ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); } else - ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); ArgOffset += ArgIncrement; // Move on to the next argument. } @@ -1800,8 +1796,7 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, Ops.push_back(DAG.getValueType(RetVT)); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - RetVal = DAG.getLoad(RetVT, Chain, StackSlot, - DAG.getSrcValue(NULL)); + RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0); Chain = RetVal.getValue(1); } @@ -1880,8 +1875,7 @@ SDOperand X86TargetLowering::LowerStdCallCCArguments(SDOperand Op, // Create the frame index object for this incoming parameter... int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); ArgValues.push_back(ArgValue); ArgOffset += ArgIncrement; // Move on to the next argument... } @@ -2086,8 +2080,7 @@ SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op, Ops.push_back(DAG.getValueType(RetVT)); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - RetVal = DAG.getLoad(RetVT, Chain, StackSlot, - DAG.getSrcValue(NULL)); + RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0); Chain = RetVal.getValue(1); } @@ -2251,11 +2244,10 @@ X86TargetLowering::LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG) { SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); if (ObjectVT == MVT::i64 && ObjIntRegs) { SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + NULL, 0); ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); } else - ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, - DAG.getSrcValue(NULL)); + ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0); ArgOffset += ArgIncrement; // Move on to the next argument. } @@ -2329,7 +2321,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, if (!isFrameAddress) // Just load the return address Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, - DAG.getSrcValue(NULL)); + NULL, 0); else Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, DAG.getConstant(4, getPointerTy())); @@ -3051,7 +3043,7 @@ static bool ShouldXformToMOVHLPS(SDNode *Mask) { static inline bool isScalarLoadToVector(SDNode *N) { if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { N = N->getOperand(0).Val; - return (N->getOpcode() == ISD::LOAD); + return ISD::isNON_EXTLoad(N); } return false; } @@ -3062,7 +3054,7 @@ static inline bool isScalarLoadToVector(SDNode *N) { /// half of V2 (and in order). And since V1 will become the source of the /// MOVLP, it must be either a vector load or a scalar load to vector. static bool ShouldXformToMOVLP(SDNode *V1, SDNode *Mask) { - if (V1->getOpcode() != ISD::LOAD && !isScalarLoadToVector(V1)) + if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) return false; unsigned NumElems = Mask->getNumOperands(); @@ -3809,10 +3801,11 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { // Use two pinsrw instructions to insert a 32 bit value. Idx <<= 1; if (MVT::isFloatingPoint(N1.getValueType())) { - if (N1.getOpcode() == ISD::LOAD) { + if (ISD::isNON_EXTLoad(N1.Val)) { // Just load directly from f32mem to GR32. - N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1), - N1.getOperand(2)); + LoadSDNode *LD = cast(N1); + N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(), + LD->getSrcValue(), LD->getSrcValueOffset()); } else { N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1); N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1); @@ -3883,14 +3876,11 @@ X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { // not the GV offset field. if (getTargetMachine().getRelocationModel() != Reloc::Static && DarwinGVRequiresExtraLoad(GV)) - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), - Result, DAG.getSrcValue(NULL)); + Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0); } else if (Subtarget->isTargetCygwin() || Subtarget->isTargetWindows()) { - // FIXME: What's about PIC? - if (WindowsGVRequiresExtraLoad(GV)) { - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), - Result, DAG.getSrcValue(NULL)); - } + // FIXME: What about PIC? + if (WindowsGVRequiresExtraLoad(GV)) + Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0); } @@ -4028,8 +4018,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { Ops.push_back(DAG.getValueType(Op.getValueType())); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, - DAG.getSrcValue(NULL)); + Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0); } return Result; @@ -4079,8 +4068,7 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size()); // Load the result. - return DAG.getLoad(Op.getValueType(), FIST, StackSlot, - DAG.getSrcValue(NULL)); + return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); } SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { @@ -4364,7 +4352,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); SDOperand Value = Op.getOperand(1); - if (Value.getOpcode() == ISD::LOAD && + if (ISD::isNON_EXTLoad(Value.Val) && (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) { Chain = Value.getOperand(0); MemLoc = Value.getOperand(1); @@ -4708,7 +4696,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { Value = DAG.getLoad(MVT::i32, Chain, DAG.getNode(ISD::ADD, SrcVT, SrcAddr, DAG.getConstant(Offset, SrcVT)), - DAG.getSrcValue(NULL)); + NULL, 0); Chain = Value.getValue(1); Chain = DAG.getStore(Chain, Value, DAG.getNode(ISD::ADD, DstVT, DstAddr, @@ -4721,7 +4709,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { Value = DAG.getLoad(MVT::i16, Chain, DAG.getNode(ISD::ADD, SrcVT, SrcAddr, DAG.getConstant(Offset, SrcVT)), - DAG.getSrcValue(NULL)); + NULL, 0); Chain = Value.getValue(1); Chain = DAG.getStore(Chain, Value, DAG.getNode(ISD::ADD, DstVT, DstAddr, @@ -4735,7 +4723,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { Value = DAG.getLoad(MVT::i8, Chain, DAG.getNode(ISD::ADD, SrcVT, SrcAddr, DAG.getConstant(Offset, SrcVT)), - DAG.getSrcValue(NULL)); + NULL, 0); Chain = Value.getValue(1); Chain = DAG.getStore(Chain, Value, DAG.getNode(ISD::ADD, DstVT, DstAddr, @@ -5328,7 +5316,7 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, } else { SDOperand Arg = getShuffleScalarElt(N, cast(Idx)->getValue(), DAG); - if (!Arg.Val || Arg.getOpcode() != ISD::LOAD) + if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val)) return SDOperand(); if (!Base) Base = Arg.Val; @@ -5339,10 +5327,11 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, } bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); - if (isAlign16) - return DAG.getLoad(VT, Base->getOperand(0), Base->getOperand(1), - Base->getOperand(2)); - else { + if (isAlign16) { + LoadSDNode *LD = cast(Base); + return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), + LD->getSrcValueOffset()); + } else { // Just use movups, it's shorter. std::vector Tys; Tys.push_back(MVT::v4f32); diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 3283ed6b479..c5089873b77 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -66,7 +66,7 @@ def fp64immneg1 : PatLeaf<(f64 fpimm), [{ return N->isExactlyValue(-1.0); }]>; -def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>; +def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>; // Some 'special' instructions let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 6798ad85b53..27c84341791 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -297,25 +297,25 @@ def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; -def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>; -def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>; -def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>; -def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>; -def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>; - -def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextload node:$ptr, i1))>; -def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>; -def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>; -def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>; -def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>; -def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>; - -def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>; -def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i1))>; -def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i1))>; -def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i8))>; -def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i8))>; -def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i16))>; +def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>; +def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>; +def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; + +def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; +def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; +def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; + +def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; //===----------------------------------------------------------------------===// // Instruction templates... diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 55f45287619..2e85167a3bb 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -467,7 +467,7 @@ def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), Requires<[HasSSE2]>; def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), "cvtss2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (extload addr:$src, f32))]>, XS, + [(set FR64:$dst, (extloadf32 addr:$src))]>, XS, Requires<[HasSSE2]>; // Match intrinsics which expect XMM operand(s). diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td index 027eb170bf7..db060e61518 100644 --- a/lib/Target/X86/X86InstrX86-64.td +++ b/lib/Target/X86/X86InstrX86-64.td @@ -84,20 +84,20 @@ def i64immSExt8 : PatLeaf<(i64 imm), [{ return (int64_t)N->getValue() == (int8_t)N->getValue(); }]>; -def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i1))>; -def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i8))>; -def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i16))>; -def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i32))>; - -def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i1))>; -def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i8))>; -def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i16))>; -def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i32))>; - -def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i1))>; -def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i8))>; -def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i16))>; -def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i32))>; +def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; //===----------------------------------------------------------------------===// // Instruction list...