From: chenxing <chenxing@rock-chips.com>
Date: Thu, 30 Aug 2012 06:56:42 +0000 (+0800)
Subject: rk3066b: add CPU_CLK_DIV
X-Git-Tag: firefly_0821_release~8765^2~15
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=467f500c6bde883f73de43ead78e86d69811f16f;p=firefly-linux-kernel-4.4.55.git

rk3066b: add CPU_CLK_DIV
---

diff --git a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
index 328d21dfedc8..594fc6dc7266 100755
--- a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
+++ b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h
@@ -109,13 +109,21 @@ enum rk_plls_id {
 #define CORE_SEL_APLL		(0 << 8)
 #define CORE_SEL_GPLL		(1 << 8)
 
-#define CORE_CLK_DIV_W_MSK	(0x1F << 16)
-#define CORE_CLK_DIV_MSK	(0x1F)
+#define CORE_CLK_DIV_W_MSK	(0x1F << 25)
+#define CORE_CLK_DIV_MSK	(0x1F << 9)
 #define CORE_CLK_DIV(i)		(((i) - 1) & 0x1F)
 
+#define CPU_SEL_PLL_MSK		(1 << 5)
+#define CPU_SEL_PLL_W_MSK	(1 << 21)
+#define CPU_SEL_APLL		(0 << 5)
+#define CPU_SEL_GPLL		(1 << 5)
+
+#define CPU_CLK_DIV_W_MSK	(0x1F << 16)
+#define CPU_CLK_DIV_MSK		(0x1F)
+#define CPU_CLK_DIV(i)		(((i) - 1) & 0x1F)
+
 /*******************CLKSEL1 BITS***************************/
 //aclk div
-
 #define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
 
 #define CPU_ACLK_W_MSK		(7 << 16)