From: Chandler Carruth Date: Fri, 5 Sep 2014 23:19:45 +0000 (+0000) Subject: [x86] Fix an embarressing bug in the INSERTPS formation code. The mask X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=469c73bc273e45970c3c9d70762d94ccd349a912;p=oota-llvm.git [x86] Fix an embarressing bug in the INSERTPS formation code. The mask computation was totally wrong, but somehow it didn't really show up with llc. I've added an assert that triggers on multiple existing test cases and updated one of them to show the correct value. There appear to still be more bugs lurking around insertps's mask. =/ However, note that this only really impacts the new vector shuffle lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217289 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 5b0d315a6d0..fab65738f70 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -7417,11 +7417,12 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2, if ((ZMask | 1 << V2Index) == 0xF) V1 = DAG.getUNDEF(MVT::v4f32); + unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask; + assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!"); + // Insert the V2 element into the desired position. - SDValue InsertPSMask = - DAG.getIntPtrConstant(Mask[V2Index] << 6 | V2Index << 4 | ZMask); return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2, - InsertPSMask); + DAG.getConstant(InsertPSMask, MVT::i8)); } } diff --git a/test/CodeGen/X86/vec_set-3.ll b/test/CodeGen/X86/vec_set-3.ll index 9823963d61b..043cf96a671 100644 --- a/test/CodeGen/X86/vec_set-3.ll +++ b/test/CodeGen/X86/vec_set-3.ll @@ -8,7 +8,7 @@ define <4 x float> @test(float %a) { ; CHECK-NEXT: retl ; ; CHECK-EXP-LABEL: test: -; CHECK-EXP: insertps $285, {{.*}}, %xmm0 +; CHECK-EXP: insertps $29, {{.*}}, %xmm0 ; CHECK-EXP-NEXT: retl entry: