From: Sean Callanan <scallanan@apple.com>
Date: Thu, 20 Aug 2009 18:24:27 +0000 (+0000)
Subject: Fixed PCMPESTRM128 to have opcode 0x60 instead of 0x62, as specified by the
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=47234e6d38407a8cfcb54ca04e45a2e657f240be;p=oota-llvm.git

Fixed PCMPESTRM128 to have opcode 0x60 instead of 0x62, as specified by the
Intel documentation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79554 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 966833f44ad..795776708e6 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -3792,11 +3792,11 @@ def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
 }
 
 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
-def PCMPESTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
+def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
 			    (ins VR128:$src1, VR128:$src3, i8imm:$src5),
 		     "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}",
 		     []>, OpSize;
-def PCMPESTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
+def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
 			    (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
 		     "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}",
 		     []>, OpSize;